| /third_party/mesa3d/src/amd/vulkan/ |
| H A D | radv_shader_info.c | 61 unsigned write_mask = nir_intrinsic_write_mask(instr); in gather_intrinsic_store_output_info() local
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| /third_party/mesa3d/src/compiler/glsl/ |
| H A D | opt_copy_propagation_elements.cpp | 95 void erase(ir_variable *var, unsigned write_mask) in erase() argument
137 void write_elements(ir_variable *lhs, ir_variable *rhs, unsigned write_mask, int swizzle[4]) in write_elements() argument
263 kill_entry(ir_variable *var, int write_mask) in kill_entry() argument
270 unsigned int write_mask; member in __anon7206::kill_entry
715 int write_mask = ir->write_mask; add_copy() local
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| H A D | glsl_to_nir.cpp | 1485 ir_constant *write_mask = ((ir_instruction *)param)->as_constant(); in visit() local
1533 ir_constant *write_mask = ((ir_instruction *)param)->as_constant(); in visit() local
1726 unsigned write_mask = ir->write_mask; in visit() local
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| H A D | ir.cpp | 83 unsigned write_mask = 0; in set_lhs() local
152 ir_assignment(ir_dereference *lhs, ir_rvalue *rhs, unsigned write_mask) ir_assignment() argument
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| /third_party/mesa3d/src/gallium/drivers/r600/sfn/ |
| H A D | sfn_shader_vs.cpp | 195 uint32_t write_mask = 0; in emit_varying_pos() local
267 int write_mask = nir_intrinsic_write_mask(&intr) << store_info.frac; in emit_varying_param() local
429 auto write_mask = nir_intrinsic_write_mask(intr); in do_scan_instruction() local
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| H A D | sfn_shader_fs.cpp | 468 unsigned write_mask = nir_intrinsic_write_mask(&intr); in emit_export_pixel() local
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| /third_party/mesa3d/src/gallium/drivers/svga/svgadump/ |
| H A D | svga_shader.h | 134 unsigned write_mask:4; member
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| /third_party/mesa3d/src/gallium/drivers/i915/ |
| H A D | i915_fpc_optimize.c | 152 is_unswizzled(struct i915_full_src_register *r, unsigned write_mask) in is_unswizzled() argument
187 set_neutral_element_swizzle(struct i915_full_src_register *r, unsigned write_mask, unsigned neutral) set_neutral_element_swizzle() argument
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| /third_party/mesa3d/src/gallium/drivers/etnaviv/ |
| H A D | etnaviv_compiler_nir.h | 104 unsigned swizzle = 0, write_mask = 0; in update_swiz_mask() local
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| H A D | etnaviv_compiler_nir.c | 691 unsigned write_mask = (1u << start_idx); in insert_vec_mov() local
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| /third_party/mesa3d/src/gallium/drivers/r600/ |
| H A D | r600_shader.h | 55 unsigned write_mask; member
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| /third_party/mesa3d/src/mesa/program/ |
| H A D | prog_to_nir.c | 261 ptn_move_dest_masked(nir_builder *b, nir_alu_dest dest, nir_ssa_def *def, unsigned write_mask) ptn_move_dest_masked() argument
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| /third_party/mesa3d/src/gallium/drivers/freedreno/a2xx/ |
| H A D | ir2_nir.c | 351 instr_create_alu_reg(struct ir2_context *ctx, nir_op opcode, uint8_t write_mask, in instr_create_alu_reg() argument
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| H A D | ir2_private.h | 126 uint8_t write_mask : 4; member
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| /kernel/linux/linux-6.6/drivers/gpu/drm/nouveau/include/nvfw/ |
| H A D | acr.h | 192 u32 write_mask; member
221 u32 write_mask; member
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| /third_party/mesa3d/src/amd/common/ |
| H A D | ac_nir_lower_tess_io_to_mem.c | 256 unsigned write_mask = nir_intrinsic_write_mask(intrin); in lower_ls_output_store() local
431 unsigned write_mask = nir_intrinsic_write_mask(intrin); in lower_hs_output_store() local
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| /third_party/mesa3d/src/compiler/nir/ |
| H A D | nir_split_vars.c | 1580 nir_component_mask_t write_mask = in shrink_vec_var_access_impl() local
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| H A D | nir_opt_copy_prop_vars.c | 111 nir_component_mask_t write_mask = nir_intrinsic_write_mask(intrin); in value_equals_store_src() local
373 lookup_entry_and_kill_aliases(struct copy_prop_var_state *state, struct util_dynarray *copies, nir_deref_and_path *deref, unsigned write_mask) lookup_entry_and_kill_aliases() argument
420 kill_aliases(struct copy_prop_var_state *state, struct util_dynarray *copies, nir_deref_and_path *deref, unsigned write_mask) kill_aliases() argument
434 get_entry_and_kill_aliases(struct copy_prop_var_state *state, struct util_dynarray *copies, nir_deref_and_path *deref, unsigned write_mask) get_entry_and_kill_aliases() argument
462 value_set_from_value(struct value *value, const struct value *from, unsigned base_index, unsigned write_mask) value_set_from_value() argument
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| H A D | nir_deref.c | 1349 nir_component_mask_t write_mask = nir_intrinsic_write_mask(store); in opt_store_vec_deref() local
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| /third_party/mesa3d/src/intel/compiler/ |
| H A D | brw_nir_rt_builder.h | 52 brw_nir_rt_store(nir_builder *b, nir_ssa_def *addr, unsigned align, nir_ssa_def *value, unsigned write_mask) brw_nir_rt_store() argument
119 brw_nir_rt_store_scratch(nir_builder *b, uint32_t offset, unsigned align, nir_ssa_def *value, nir_component_mask_t write_mask) brw_nir_rt_store_scratch() argument
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| H A D | brw_vec4_generator.cpp | 854 generate_tcs_output_urb_offsets(struct brw_codegen *p, struct brw_reg dst, struct brw_reg write_mask, struct brw_reg offset) generate_tcs_output_urb_offsets() argument
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| /third_party/mesa3d/src/panfrost/midgard/ |
| H A D | midgard_ra.c | 962 unsigned write_mask = mir_from_bytemask(mir_round_bytemask_up( in mir_spill_register() local
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| /kernel/linux/linux-5.10/drivers/infiniband/hw/hfi1/ |
| H A D | driver.c | 121 write_mask = ((HFI1_CAP_WRITABLE_MASK << HFI1_CAP_USER_SHIFT) | in hfi1_caps_set() local
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| /kernel/linux/linux-5.10/drivers/gpu/drm/rockchip/ |
| H A D | rockchip_drm_vop.h | 49 bool write_mask; member
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| /kernel/linux/linux-6.6/drivers/infiniband/hw/hfi1/ |
| H A D | driver.c | 74 write_mask = ((HFI1_CAP_WRITABLE_MASK << HFI1_CAP_USER_SHIFT) | in hfi1_caps_set() local
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