| /third_party/ltp/tools/sparse/sparse-src/validation/optim/ |
| H A D | binops-same-args.c | 7 u32 udiv(u32 a) { return a / a; } in udiv() function
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| /third_party/ltp/tools/sparse/sparse-src/validation/backend/ |
| H A D | arithmetic-ops.c | 66 static unsigned int udiv(unsigned int x, unsigned int y) in udiv() function
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| /third_party/mesa3d/src/util/tests/ |
| H A D | fast_idiv_by_const_test.cpp | 237 udiv(uint64_t a, uint64_t b, unsigned bit_size) in udiv() function
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| /kernel/linux/linux-5.10/arch/powerpc/boot/ |
| H A D | cuboot-acadia.c | 49 unsigned long udiv; /* best udiv */ in get_clocks() local
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| H A D | 4xx.c | 555 u32 fwdv, fwdvb, fbdv, cbdv, opdv, epdv, ppdv, udiv; in ibm405gp_fixup_clocks() local
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| /kernel/linux/linux-6.6/arch/powerpc/boot/ |
| H A D | cuboot-acadia.c | 49 unsigned long udiv; /* best udiv */ in get_clocks() local
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| H A D | 4xx.c | 555 u32 fwdv, fwdvb, fbdv, cbdv, opdv, epdv, ppdv, udiv; in ibm405gp_fixup_clocks() local
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| /third_party/vixl/src/aarch64/ |
| H A D | logic-aarch64.cc | 671 LogicVRegister Simulator::udiv(VectorFormat vform, in udiv() function in vixl::aarch64::Simulator
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| H A D | assembler-aarch64.cc | 1003 void Assembler::udiv(const Register& rd, in udiv() function in vixl::aarch64::Assembler
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| H A D | assembler-sve-aarch64.cc | 2576 void Assembler::udiv(const ZRegister& zd, in udiv() function in vixl::aarch64::Assembler
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| /third_party/skia/third_party/externals/swiftshader/src/Shader/ |
| H A D | ShaderCore.cpp | 861 void ShaderCore::udiv(Vector4f &dst, const Vector4f &src0, const Vector4f &src1) in udiv() function in sw::ShaderCore
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| /third_party/node/deps/v8/src/codegen/arm64/ |
| H A D | assembler-arm64.cc | 1160 void Assembler::udiv(const Register& rd, const Register& rn, in udiv() function in v8::internal::Assembler
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| /third_party/node/deps/v8/src/codegen/arm/ |
| H A D | assembler-arm.cc | 1755 void Assembler::udiv(Register dst, Register src1, Register src2, in udiv() function in v8::internal::Assembler
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| /third_party/vixl/src/aarch32/ |
| H A D | assembler-aarch32.cc | 13075 void Assembler::udiv(Condition cond, Register rd, Register rn, Register rm) { in udiv() function in vixl::aarch32::Assembler
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| H A D | assembler-aarch32.h | 3644 void udiv(Register rd, Register rn, Register rm) { udiv(al, rd, rn, rm); } in udiv() function in vixl::aarch32::Assembler
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| H A D | disasm-aarch32.cc | 3374 void Disassembler::udiv(Condition cond, Register rd, Register rn, Register rm) { in udiv() function in vixl::aarch32::Disassembler
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