| /third_party/node/deps/v8/src/codegen/mips/ |
| H A D | macro-assembler-mips.cc | 106 LoadRoot(Register destination, RootIndex index, Condition cond, Register src1, const Operand& src2) LoadRoot() argument
4277 MovToFloatParameters(DoubleRegister src1, DoubleRegister src2) CallRecordWriteStub() argument
5146 Float32Max(FPURegister dst, FPURegister src1, FPURegister src2, Label* out_of_line) CallRecordWriteStub() argument
5191 Float32MaxOutOfLine(FPURegister dst, FPURegister src1, FPURegister src2) CallRecordWriteStub() argument
5196 Float32Min(FPURegister dst, FPURegister src1, FPURegister src2, Label* out_of_line) CallRecordWriteStub() argument
5241 Float32MinOutOfLine(FPURegister dst, FPURegister src1, FPURegister src2) CallRecordWriteStub() argument
5246 Float64Max(DoubleRegister dst, DoubleRegister src1, DoubleRegister src2, Label* out_of_line) CallRecordWriteStub() argument
5291 Float64MaxOutOfLine(DoubleRegister dst, DoubleRegister src1, DoubleRegister src2) CallRecordWriteStub() argument
5297 Float64Min(DoubleRegister dst, DoubleRegister src1, DoubleRegister src2, Label* out_of_line) CallRecordWriteStub() argument
5342 Float64MinOutOfLine(DoubleRegister dst, DoubleRegister src1, DoubleRegister src2) CallRecordWriteStub() argument
[all...] |
| H A D | assembler-mips.cc | 2927 void Assembler::fcmp(FPURegister src1, const double src2, FPUCondition cond) { in fcmp() argument
|
| /third_party/node/deps/v8/src/codegen/riscv64/ |
| H A D | macro-assembler-riscv64.cc | 101 LoadRoot(Register destination, RootIndex index, Condition cond, Register src1, const Operand& src2) LoadRoot() argument
3650 MovToFloatParameters(DoubleRegister src1, DoubleRegister src2) MovToFloatParameters() argument
4709 FloatMinMaxHelper(FPURegister dst, FPURegister src1, FPURegister src2, MaxMinKind kind) FloatMinMaxHelper() argument
4764 Float32Max(FPURegister dst, FPURegister src1, FPURegister src2) Float32Max() argument
4770 Float32Min(FPURegister dst, FPURegister src1, FPURegister src2) Float32Min() argument
4776 Float64Max(FPURegister dst, FPURegister src1, FPURegister src2) Float64Max() argument
4782 Float64Min(FPURegister dst, FPURegister src1, FPURegister src2) Float64Min() argument
[all...] |
| /third_party/node/deps/v8/src/codegen/arm/ |
| H A D | assembler-arm.cc | 1536 void Assembler::and_(Register dst, Register src1, const Operand& src2, SBit s, in and_() argument
1541 void Assembler::and_(Register dst, Register src1, Register src2, SBit s, in and_() argument
1546 void Assembler::eor(Register dst, Register src1, const Operand& src2, SBit s, in eor() argument
1551 void Assembler::eor(Register dst, Register src1, Register src2, SBit s, in eor() argument
1556 void Assembler::sub(Register dst, Register src1, const Operand& src2, SBit s, in sub() argument
1561 sub(Register dst, Register src1, Register src2, SBit s, Condition cond) sub() argument
1566 rsb(Register dst, Register src1, const Operand& src2, SBit s, Condition cond) rsb() argument
1571 add(Register dst, Register src1, const Operand& src2, SBit s, Condition cond) add() argument
1576 add(Register dst, Register src1, Register src2, SBit s, Condition cond) add() argument
1581 adc(Register dst, Register src1, const Operand& src2, SBit s, Condition cond) adc() argument
1586 sbc(Register dst, Register src1, const Operand& src2, SBit s, Condition cond) sbc() argument
1591 rsc(Register dst, Register src1, const Operand& src2, SBit s, Condition cond) rsc() argument
1596 tst(Register src1, const Operand& src2, Condition cond) tst() argument
1600 tst(Register src1, Register src2, Condition cond) tst() argument
1604 teq(Register src1, const Operand& src2, Condition cond) teq() argument
1608 cmp(Register src1, const Operand& src2, Condition cond) cmp() argument
1612 cmp(Register src1, Register src2, Condition cond) cmp() argument
1622 cmn(Register src1, const Operand& src2, Condition cond) cmn() argument
1626 orr(Register dst, Register src1, const Operand& src2, SBit s, Condition cond) orr() argument
1631 orr(Register dst, Register src1, Register src2, SBit s, Condition cond) orr() argument
1695 bic(Register dst, Register src1, const Operand& src2, SBit s, Condition cond) bic() argument
1704 asr(Register dst, Register src1, const Operand& src2, SBit s, Condition cond) asr() argument
1713 lsl(Register dst, Register src1, const Operand& src2, SBit s, Condition cond) lsl() argument
1722 lsr(Register dst, Register src1, const Operand& src2, SBit s, Condition cond) lsr() argument
1732 mla(Register dst, Register src1, Register src2, Register srcA, SBit s, Condition cond) mla() argument
1739 mls(Register dst, Register src1, Register src2, Register srcA, Condition cond) mls() argument
1747 sdiv(Register dst, Register src1, Register src2, Condition cond) sdiv() argument
1755 udiv(Register dst, Register src1, Register src2, Condition cond) udiv() argument
1763 mul(Register dst, Register src1, Register src2, SBit s, Condition cond) mul() argument
1770 smmla(Register dst, Register src1, Register src2, Register srcA, Condition cond) smmla() argument
1777 smmul(Register dst, Register src1, Register src2, Condition cond) smmul() argument
1784 smlal(Register dstL, Register dstH, Register src1, Register src2, SBit s, Condition cond) smlal() argument
1792 smull(Register dstL, Register dstH, Register src1, Register src2, SBit s, Condition cond) smull() argument
1800 umlal(Register dstL, Register dstH, Register src1, Register src2, SBit s, Condition cond) umlal() argument
1808 umull(Register dstL, Register dstH, Register src1, Register src2, SBit s, Condition cond) umull() argument
1901 pkhbt(Register dst, Register src1, const Operand& src2, Condition cond) pkhbt() argument
1916 pkhtb(Register dst, Register src1, const Operand& src2, Condition cond) pkhtb() argument
1943 sxtab(Register dst, Register src1, Register src2, int rotate, Condition cond) sxtab() argument
1967 sxtah(Register dst, Register src1, Register src2, int rotate, Condition cond) sxtah() argument
1991 uxtab(Register dst, Register src1, Register src2, int rotate, Condition cond) uxtab() argument
2026 uxtah(Register dst, Register src1, Register src2, int rotate, Condition cond) uxtah() argument
2131 strd(Register src1, Register src2, const MemOperand& dst, Condition cond) strd() argument
2159 strex(Register src1, Register src2, Register dst, Condition cond) strex() argument
2182 strexb(Register src1, Register src2, Register dst, Condition cond) strexb() argument
2205 strexh(Register src1, Register src2, Register dst, Condition cond) strexh() argument
2231 strexd(Register res, Register src1, Register src2, Register dst, Condition cond) strexd() argument
2908 vmov(const DwVfpRegister dst, const Register src1, const Register src2, const Condition cond) vmov() argument
3186 vadd(const DwVfpRegister dst, const DwVfpRegister src1, const DwVfpRegister src2, const Condition cond) vadd() argument
3206 vadd(const SwVfpRegister dst, const SwVfpRegister src1, const SwVfpRegister src2, const Condition cond) vadd() argument
3223 vsub(const DwVfpRegister dst, const DwVfpRegister src1, const DwVfpRegister src2, const Condition cond) vsub() argument
3243 vsub(const SwVfpRegister dst, const SwVfpRegister src1, const SwVfpRegister src2, const Condition cond) vsub() argument
3260 vmul(const DwVfpRegister dst, const DwVfpRegister src1, const DwVfpRegister src2, const Condition cond) vmul() argument
3280 vmul(const SwVfpRegister dst, const SwVfpRegister src1, const SwVfpRegister src2, const Condition cond) vmul() argument
3297 vmla(const DwVfpRegister dst, const DwVfpRegister src1, const DwVfpRegister src2, const Condition cond) vmla() argument
3315 vmla(const SwVfpRegister dst, const SwVfpRegister src1, const SwVfpRegister src2, const Condition cond) vmla() argument
3330 vmls(const DwVfpRegister dst, const DwVfpRegister src1, const DwVfpRegister src2, const Condition cond) vmls() argument
3348 vmls(const SwVfpRegister dst, const SwVfpRegister src1, const SwVfpRegister src2, const Condition cond) vmls() argument
3363 vdiv(const DwVfpRegister dst, const DwVfpRegister src1, const DwVfpRegister src2, const Condition cond) vdiv() argument
3383 vdiv(const SwVfpRegister dst, const SwVfpRegister src1, const SwVfpRegister src2, const Condition cond) vdiv() argument
3400 vcmp(const DwVfpRegister src1, const DwVfpRegister src2, const Condition cond) vcmp() argument
3416 vcmp(const SwVfpRegister src1, const SwVfpRegister src2, const Condition cond) vcmp() argument
3430 vcmp(const DwVfpRegister src1, const double src2, const Condition cond) vcmp() argument
3444 vcmp(const SwVfpRegister src1, const float src2, const Condition cond) vcmp() argument
3457 vmaxnm(const DwVfpRegister dst, const DwVfpRegister src1, const DwVfpRegister src2) vmaxnm() argument
3473 vmaxnm(const SwVfpRegister dst, const SwVfpRegister src1, const SwVfpRegister src2) vmaxnm() argument
3489 vminnm(const DwVfpRegister dst, const DwVfpRegister src1, const DwVfpRegister src2) vminnm() argument
3505 vminnm(const SwVfpRegister dst, const SwVfpRegister src1, const SwVfpRegister src2) vminnm() argument
3521 vsel(Condition cond, const DwVfpRegister dst, const DwVfpRegister src1, const DwVfpRegister src2) vsel() argument
3553 vsel(Condition cond, const SwVfpRegister dst, const SwVfpRegister src1, const SwVfpRegister src2) vsel() argument
4263 vand(QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2) vand() argument
4272 vbic(QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2) vbic() argument
4281 vbsl(QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2) vbsl() argument
4290 veor(DwVfpRegister dst, DwVfpRegister src1, DwVfpRegister src2) veor() argument
4299 veor(QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2) veor() argument
4308 vorr(QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2) vorr() argument
4317 vorn(QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2) vorn() argument
4339 EncodeNeonBinOp(FPBinOp op, QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2) EncodeNeonBinOp() argument
4402 EncodeNeonBinOp(IntegerBinOp op, NeonDataType dt, QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2) EncodeNeonBinOp() argument
4461 EncodeNeonBinOp(IntegerBinOp op, NeonSize size, QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2) EncodeNeonBinOp() argument
4468 vadd(QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2) vadd() argument
4476 vadd(NeonSize size, QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2) vadd() argument
4484 vqadd(NeonDataType dt, QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2) vqadd() argument
4492 vsub(QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2) vsub() argument
4500 vsub(NeonSize size, QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2) vsub() argument
4508 vqsub(NeonDataType dt, QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2) vqsub() argument
4516 vmlal(NeonDataType dt, QwNeonRegister dst, DwVfpRegister src1, DwVfpRegister src2) vmlal() argument
4535 vmul(QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2) vmul() argument
4543 vmul(NeonSize size, QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2) vmul() argument
4551 vmull(NeonDataType dt, QwNeonRegister dst, DwVfpRegister src1, DwVfpRegister src2) vmull() argument
4568 vmin(QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2) vmin() argument
4576 vmin(NeonDataType dt, QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2) vmin() argument
4584 vmax(QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2) vmax() argument
4592 vmax(NeonDataType dt, QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2) vmax() argument
4750 vrecps(QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2) vrecps() argument
4758 vrsqrts(QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2) vrsqrts() argument
4768 EncodeNeonPairwiseOp(NeonPairwiseOp op, NeonDataType dt, DwVfpRegister dst, DwVfpRegister src1, DwVfpRegister src2) EncodeNeonPairwiseOp() argument
4797 vpadd(DwVfpRegister dst, DwVfpRegister src1, DwVfpRegister src2) vpadd() argument
4813 vpadd(NeonSize size, DwVfpRegister dst, DwVfpRegister src1, DwVfpRegister src2) vpadd() argument
4821 vpmin(NeonDataType dt, DwVfpRegister dst, DwVfpRegister src1, DwVfpRegister src2) vpmin() argument
4829 vpmax(NeonDataType dt, DwVfpRegister dst, DwVfpRegister src1, DwVfpRegister src2) vpmax() argument
4869 vtst(NeonSize size, QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2) vtst() argument
4877 vceq(QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2) vceq() argument
4885 vceq(NeonSize size, QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2) vceq() argument
4902 vcge(QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2) vcge() argument
4910 vcge(NeonDataType dt, QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2) vcge() argument
4918 vcgt(QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2) vcgt() argument
4926 vcgt(NeonDataType dt, QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2) vcgt() argument
4943 vrhadd(NeonDataType dt, QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2) vrhadd() argument
4951 vext(QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2, int bytes) vext() argument
4967 vzip(NeonSize size, DwVfpRegister src1, DwVfpRegister src2) vzip() argument
4978 vzip(NeonSize size, QwNeonRegister src1, QwNeonRegister src2) vzip() argument
4985 vuzp(NeonSize size, DwVfpRegister src1, DwVfpRegister src2) vuzp() argument
4996 vuzp(NeonSize size, QwNeonRegister src1, QwNeonRegister src2) vuzp() argument
5024 vtrn(NeonSize size, DwVfpRegister src1, DwVfpRegister src2) vtrn() argument
5031 vtrn(NeonSize size, QwNeonRegister src1, QwNeonRegister src2) vtrn() argument
5054 vqrdmulh(NeonDataType dt, QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2) vqrdmulh() argument
[all...] |
| /third_party/node/deps/v8/src/execution/arm/ |
| H A D | simulator-arm.cc | 3949 T src1[kLanes], src2[kLanes]; in Binop() local
4017 T src1[kElems], src2[kElems], dst1[kElems], dst2[kElems]; in Zip() local
4034 T src1[kElems], src2[kElems], dst1[kElems], dst2[kElems]; in Unzip() local
4051 T src1[kElems], src2[kElems]; Transpose() local
4125 T src1[kElems], src2[kElems]; Mul() local
4276 T dst[kElems], src1[kElems], src2[kElems]; PairwiseMinMax() local
4290 T dst[kElems], src1[kElems], src2[kElems]; PairwiseAdd() local
4333 NarrowType src1[kElems], src2[kElems]; MultiplyLong() local
4384 uint8_t src1[16], src2[16], dst[16]; DecodeAdvancedSIMDTwoOrThreeRegisters() local
4979 uint64_t src1, src2, dst[2]; DecodeAdvancedSIMDTwoOrThreeRegisters() local
5082 uint32_t src2[4]; DecodeAdvancedSIMDDataProcessing() local
5096 uint32_t src1[4], src2[4]; DecodeAdvancedSIMDDataProcessing() local
5105 uint32_t src1[4], src2[4]; DecodeAdvancedSIMDDataProcessing() local
5267 float src1[4], src2[4]; DecodeAdvancedSIMDDataProcessing() local
5282 float src1[4], src2[4]; DecodeAdvancedSIMDDataProcessing() local
5291 float src1[4], src2[4]; DecodeAdvancedSIMDDataProcessing() local
5307 float src1[4], src2[4]; DecodeAdvancedSIMDDataProcessing() local
5338 uint32_t dst[4], src1[4], src2[4]; DecodeAdvancedSIMDDataProcessing() local
5348 uint64_t src1, src2; DecodeAdvancedSIMDDataProcessing() local
5355 uint32_t src1[4], src2[4]; DecodeAdvancedSIMDDataProcessing() local
5497 float src1[4], src2[4]; DecodeAdvancedSIMDDataProcessing() local
5510 float src1[4], src2[4]; DecodeAdvancedSIMDDataProcessing() local
[all...] |
| /third_party/node/deps/v8/src/wasm/baseline/x64/ |
| H A D | liftoff-assembler-x64.h | 2868 emit_s128_select(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2, LiftoffRegister mask) emit_s128_select() argument
3161 emit_i16x8_extmul_low_i8x16_s(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2) emit_i16x8_extmul_low_i8x16_s() argument
3168 emit_i16x8_extmul_low_i8x16_u(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2) emit_i16x8_extmul_low_i8x16_u() argument
3175 emit_i16x8_extmul_high_i8x16_s(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2) emit_i16x8_extmul_high_i8x16_s() argument
3181 emit_i16x8_extmul_high_i8x16_u(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2) emit_i16x8_extmul_high_i8x16_u() argument
3187 emit_i16x8_q15mulr_sat_s(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2) emit_i16x8_q15mulr_sat_s() argument
3318 I32x4ExtMulHelper(LiftoffAssembler* assm, XMMRegister dst, XMMRegister src1, XMMRegister src2, bool low, bool is_signed) I32x4ExtMulHelper() argument
3337 emit_i32x4_extmul_low_i16x8_s(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2) emit_i32x4_extmul_low_i16x8_s() argument
3344 emit_i32x4_extmul_low_i16x8_u(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2) emit_i32x4_extmul_low_i16x8_u() argument
3351 emit_i32x4_extmul_high_i16x8_s(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2) emit_i32x4_extmul_high_i16x8_s() argument
3359 emit_i32x4_extmul_high_i16x8_u(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2) emit_i32x4_extmul_high_i16x8_u() argument
3436 emit_i64x2_extmul_low_i32x4_s(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2) emit_i64x2_extmul_low_i32x4_s() argument
3443 emit_i64x2_extmul_low_i32x4_u(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2) emit_i64x2_extmul_low_i32x4_u() argument
3450 emit_i64x2_extmul_high_i32x4_s(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2) emit_i64x2_extmul_high_i32x4_s() argument
3457 emit_i64x2_extmul_high_i32x4_u(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2) emit_i64x2_extmul_high_i32x4_u() argument
3930 emit_i8x16_replace_lane(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2, uint8_t imm_lane_idx) emit_i8x16_replace_lane() argument
3944 emit_i16x8_replace_lane(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2, uint8_t imm_lane_idx) emit_i16x8_replace_lane() argument
3957 emit_i32x4_replace_lane(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2, uint8_t imm_lane_idx) emit_i32x4_replace_lane() argument
3971 emit_i64x2_replace_lane(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2, uint8_t imm_lane_idx) emit_i64x2_replace_lane() argument
3985 emit_f32x4_replace_lane(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2, uint8_t imm_lane_idx) emit_f32x4_replace_lane() argument
3999 emit_f64x2_replace_lane(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2, uint8_t imm_lane_idx) emit_f64x2_replace_lane() argument
[all...] |
| /third_party/node/deps/v8/src/wasm/baseline/riscv64/ |
| H A D | liftoff-assembler-riscv64.h | 2002 emit_i64x2_extmul_low_i32x4_s(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2) emit_i64x2_extmul_low_i32x4_s() argument
2017 emit_i64x2_extmul_low_i32x4_u(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2) emit_i64x2_extmul_low_i32x4_u() argument
2032 emit_i64x2_extmul_high_i32x4_s(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2) emit_i64x2_extmul_high_i32x4_s() argument
2042 emit_i64x2_extmul_high_i32x4_u(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2) emit_i64x2_extmul_high_i32x4_u() argument
2052 emit_i32x4_extmul_low_i16x8_s(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2) emit_i32x4_extmul_low_i16x8_s() argument
2067 emit_i32x4_extmul_low_i16x8_u(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2) emit_i32x4_extmul_low_i16x8_u() argument
2082 emit_i32x4_extmul_high_i16x8_s(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2) emit_i32x4_extmul_high_i16x8_s() argument
2092 emit_i32x4_extmul_high_i16x8_u(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2) emit_i32x4_extmul_high_i16x8_u() argument
2102 emit_i16x8_extmul_low_i8x16_s(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2) emit_i16x8_extmul_low_i8x16_s() argument
2117 emit_i16x8_extmul_low_i8x16_u(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2) emit_i16x8_extmul_low_i8x16_u() argument
2132 emit_i16x8_extmul_high_i8x16_s(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2) emit_i16x8_extmul_high_i8x16_s() argument
2142 emit_i16x8_extmul_high_i8x16_u(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2) emit_i16x8_extmul_high_i8x16_u() argument
2154 emit_i16x8_q15mulr_sat_s(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2) emit_i16x8_q15mulr_sat_s() argument
2459 emit_s128_select(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2, LiftoffRegister mask) emit_s128_select() argument
3546 emit_i8x16_replace_lane(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2, uint8_t imm_lane_idx) emit_i8x16_replace_lane() argument
3557 emit_i16x8_replace_lane(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2, uint8_t imm_lane_idx) emit_i16x8_replace_lane() argument
3567 emit_i32x4_replace_lane(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2, uint8_t imm_lane_idx) emit_i32x4_replace_lane() argument
3577 emit_i64x2_replace_lane(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2, uint8_t imm_lane_idx) emit_i64x2_replace_lane() argument
3587 emit_f32x4_replace_lane(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2, uint8_t imm_lane_idx) emit_f32x4_replace_lane() argument
3598 emit_f64x2_replace_lane(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2, uint8_t imm_lane_idx) emit_f64x2_replace_lane() argument
[all...] |
| /third_party/node/deps/v8/src/wasm/baseline/mips64/ |
| H A D | liftoff-assembler-mips64.h | 2219 emit_i16x8_q15mulr_sat_s(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2) emit_i16x8_q15mulr_sat_s() argument
2412 emit_s128_select(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2, LiftoffRegister mask) emit_s128_select() argument
3368 emit_i8x16_replace_lane(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2, uint8_t imm_lane_idx) emit_i8x16_replace_lane() argument
3378 emit_i16x8_replace_lane(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2, uint8_t imm_lane_idx) emit_i16x8_replace_lane() argument
3388 emit_i32x4_replace_lane(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2, uint8_t imm_lane_idx) emit_i32x4_replace_lane() argument
3398 emit_i64x2_replace_lane(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2, uint8_t imm_lane_idx) emit_i64x2_replace_lane() argument
3408 emit_f32x4_replace_lane(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2, uint8_t imm_lane_idx) emit_f32x4_replace_lane() argument
3419 emit_f64x2_replace_lane(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2, uint8_t imm_lane_idx) emit_f64x2_replace_lane() argument
[all...] |
| /third_party/mesa3d/src/panfrost/midgard/ |
| H A D | midgard.h | 317 unsigned src2 : 13; member
339 unsigned src2 : 11; member
|
| /third_party/icu/ohos_icu4c/src/ |
| H A D | icu_addon.cpp | 1556 int32_t ucol_mergeSortkeys(const uint8_t *src1, int32_t src1Length, const uint8_t *src2, int32_t src2Length, in ucol_mergeSortkeys() argument
|
| /third_party/mesa3d/src/gallium/drivers/svga/ |
| H A D | svga_tgsi_vgpu10.c | 6487 emit_instruction_opn(struct svga_shader_emitter_v10 *emit, unsigned opcode, const struct tgsi_full_dst_register *dst, const struct tgsi_full_src_register *src1, const struct tgsi_full_src_register *src2, const struct tgsi_full_src_register *src3, boolean saturate, bool precise) emit_instruction_opn() argument
6518 emit_instruction_op2(struct svga_shader_emitter_v10 *emit, VGPU10_OPCODE_TYPE opcode, const struct tgsi_full_dst_register *dst, const struct tgsi_full_src_register *src1, const struct tgsi_full_src_register *src2) emit_instruction_op2() argument
6528 emit_instruction_op3(struct svga_shader_emitter_v10 *emit, VGPU10_OPCODE_TYPE opcode, const struct tgsi_full_dst_register *dst, const struct tgsi_full_src_register *src1, const struct tgsi_full_src_register *src2, const struct tgsi_full_src_register *src3) emit_instruction_op3() argument
9401 struct tgsi_full_src_register src2 = check_double_src(emit, &inst->Src[2]); emit_dmad() local
[all...] |
| /third_party/vixl/src/aarch64/ |
| H A D | simulator-aarch64.cc | 2165 uint64_t src2 = ReadXRegister(instr->GetRm()); in Simulator() local
11358 uint64_t src2 = is_64_bit ? ReadXRegister(rm_code) : ReadWRegister(rm_code); in Simulator() local
11406 SimVRegister src2; in Simulator() local
11444 SimVRegister src2; Simulator() local
[all...] |