| /third_party/node/deps/v8/src/codegen/ppc/ |
| H A D | assembler-ppc.cc | 798 void Assembler::addc(Register dst, Register src1, Register src2, OEBit o, in addc() argument
803 void Assembler::adde(Register dst, Register src1, Register src2, OEBit o, in adde() argument
808 void Assembler::addze(Register dst, Register src1, OEBit o, RCBit r) { in addze() argument
813 void Assembler::sub(Register dst, Register src1, Register src2, OEBit o, in sub() argument
818 void Assembler::subc(Register dst, Register src1, Register src2, OEBit o, in subc() argument
823 sube(Register dst, Register src1, Register src2, OEBit o, RCBit r) sube() argument
832 add(Register dst, Register src1, Register src2, OEBit o, RCBit r) add() argument
838 mullw(Register dst, Register src1, Register src2, OEBit o, RCBit r) mullw() argument
848 mulhw(Register dst, Register src1, Register src2, RCBit r) mulhw() argument
853 mulhwu(Register dst, Register src1, Register src2, RCBit r) mulhwu() argument
858 divw(Register dst, Register src1, Register src2, OEBit o, RCBit r) divw() argument
864 divwu(Register dst, Register src1, Register src2, OEBit o, RCBit r) divwu() argument
899 cmpi(Register src1, const Operand& src2, CRegister cr) cmpi() argument
912 cmpli(Register src1, const Operand& src2, CRegister cr) cmpli() argument
925 cmpwi(Register src1, const Operand& src2, CRegister cr) cmpwi() argument
942 cmplwi(Register src1, const Operand& src2, CRegister cr) cmplwi() argument
1128 mulld(Register dst, Register src1, Register src2, OEBit o, RCBit r) mulld() argument
1133 divd(Register dst, Register src1, Register src2, OEBit o, RCBit r) divd() argument
1138 divdu(Register dst, Register src1, Register src2, OEBit o, RCBit r) divdu() argument
[all...] |
| /third_party/node/deps/v8/src/codegen/ia32/ |
| H A D | assembler-ia32.cc | 2865 void Assembler::vss(byte op, XMMRegister dst, XMMRegister src1, Operand src2) { in vss() argument
2869 void Assembler::vps(byte op, XMMRegister dst, XMMRegister src1, Operand src2) { in vps() argument
2873 void Assembler::vpd(byte op, XMMRegister dst, XMMRegister src1, Operand src2) { in vpd() argument
2877 void Assembler::vshufpd(XMMRegister dst, XMMRegister src1, Operand src2, in vshufpd() argument
2884 void Assembler::vmovhlps(XMMRegister dst, XMMRegister src1, XMMRegister src2) { in vmovhlps() argument
2888 vmovlhps(XMMRegister dst, XMMRegister src1, XMMRegister src2) vmovlhps() argument
2892 vmovlps(XMMRegister dst, XMMRegister src1, Operand src2) vmovlps() argument
2900 vmovhps(XMMRegister dst, XMMRegister src1, Operand src2) vmovhps() argument
2908 vcmpps(XMMRegister dst, XMMRegister src1, Operand src2, uint8_t cmp) vcmpps() argument
2914 vcmppd(XMMRegister dst, XMMRegister src1, Operand src2, uint8_t cmp) vcmppd() argument
2920 vshufps(XMMRegister dst, XMMRegister src1, Operand src2, byte imm8) vshufps() argument
2990 vblendvps(XMMRegister dst, XMMRegister src1, XMMRegister src2, XMMRegister mask) vblendvps() argument
2996 vblendvpd(XMMRegister dst, XMMRegister src1, XMMRegister src2, XMMRegister mask) vblendvpd() argument
3002 vpblendvb(XMMRegister dst, XMMRegister src1, XMMRegister src2, XMMRegister mask) vpblendvb() argument
3008 vpblendw(XMMRegister dst, XMMRegister src1, Operand src2, uint8_t mask) vpblendw() argument
3014 vpalignr(XMMRegister dst, XMMRegister src1, Operand src2, uint8_t mask) vpalignr() argument
3035 vinsertps(XMMRegister dst, XMMRegister src1, Operand src2, uint8_t offset) vinsertps() argument
3041 vpinsrb(XMMRegister dst, XMMRegister src1, Operand src2, uint8_t offset) vpinsrb() argument
3047 vpinsrw(XMMRegister dst, XMMRegister src1, Operand src2, uint8_t offset) vpinsrw() argument
3053 vpinsrd(XMMRegister dst, XMMRegister src1, Operand src2, uint8_t offset) vpinsrd() argument
3059 vroundsd(XMMRegister dst, XMMRegister src1, XMMRegister src2, RoundingMode mode) vroundsd() argument
3064 vroundss(XMMRegister dst, XMMRegister src1, XMMRegister src2, RoundingMode mode) vroundss() argument
3107 vpcmpgtq(XMMRegister dst, XMMRegister src1, XMMRegister src2) vpcmpgtq() argument
3205 vinstr(byte op, XMMRegister dst, XMMRegister src1, XMMRegister src2, SIMDPrefix pp, LeadingOpcode m, VexW w, CpuFeature feature) vinstr() argument
3211 vinstr(byte op, XMMRegister dst, XMMRegister src1, Operand src2, SIMDPrefix pp, LeadingOpcode m, VexW w, CpuFeature feature) vinstr() argument
3217 vinstr(byte op, XMMRegister dst, XMMRegister src1, XMMRegister src2, VectorLength l, SIMDPrefix pp, LeadingOpcode m, VexW w, CpuFeature feature) vinstr() argument
3227 vinstr(byte op, XMMRegister dst, XMMRegister src1, Operand src2, VectorLength l, SIMDPrefix pp, LeadingOpcode m, VexW w, CpuFeature feature) vinstr() argument
[all...] |
| /third_party/node/deps/v8/src/codegen/loong64/ |
| H A D | macro-assembler-loong64.cc | 3814 void TurboAssembler::Float32Max(FPURegister dst, FPURegister src1, in CallRecordWriteStub() argument
3829 void TurboAssembler::Float32MaxOutOfLine(FPURegister dst, FPURegister src1, in CallRecordWriteStub() argument
3834 void TurboAssembler::Float32Min(FPURegister dst, FPURegister src1, in CallRecordWriteStub() argument
3849 Float32MinOutOfLine(FPURegister dst, FPURegister src1, FPURegister src2) CallRecordWriteStub() argument
3854 Float64Max(FPURegister dst, FPURegister src1, FPURegister src2, Label* out_of_line) CallRecordWriteStub() argument
3869 Float64MaxOutOfLine(FPURegister dst, FPURegister src1, FPURegister src2) CallRecordWriteStub() argument
3874 Float64Min(FPURegister dst, FPURegister src1, FPURegister src2, Label* out_of_line) CallRecordWriteStub() argument
3889 Float64MinOutOfLine(FPURegister dst, FPURegister src1, FPURegister src2) CallRecordWriteStub() argument
[all...] |
| /third_party/node/deps/v8/src/codegen/x64/ |
| H A D | assembler-x64.cc | 3523 void Assembler::fma_instr(byte op, XMMRegister dst, XMMRegister src1, in fma_instr() argument
3533 void Assembler::fma_instr(byte op, XMMRegister dst, XMMRegister src1, in fma_instr() argument
3675 void Assembler::vmovlps(XMMRegister dst, XMMRegister src1, Operand src2) { in vmovlps() argument
3691 void Assembler::vmovhps(XMMRegister dst, XMMRegister src1, Operand src2) { in vmovhps() argument
3707 void Assembler::vinstr(byte op, XMMRegister dst, XMMRegister src1, in vinstr() argument
3718 vinstr(byte op, XMMRegister dst, XMMRegister src1, Operand src2, SIMDPrefix pp, LeadingOpcode m, VexW w, CpuFeature feature) vinstr() argument
3730 vinstr(byte op, Reg1 dst, Reg2 src1, Op src2, SIMDPrefix pp, LeadingOpcode m, VexW w, CpuFeature feature) vinstr() argument
3756 vps(byte op, XMMRegister dst, XMMRegister src1, XMMRegister src2) vps() argument
3765 vps(byte op, YMMRegister dst, YMMRegister src1, YMMRegister src2) vps() argument
3774 vps(byte op, XMMRegister dst, XMMRegister src1, Operand src2) vps() argument
3782 vps(byte op, YMMRegister dst, YMMRegister src1, Operand src2) vps() argument
3790 vps(byte op, XMMRegister dst, XMMRegister src1, XMMRegister src2, byte imm8) vps() argument
3800 vps(byte op, YMMRegister dst, YMMRegister src1, YMMRegister src2, byte imm8) vps() argument
3857 vss(byte op, XMMRegister dst, XMMRegister src1, XMMRegister src2) vss() argument
3866 vss(byte op, XMMRegister dst, XMMRegister src1, Operand src2) vss() argument
[all...] |
| H A D | macro-assembler-x64.cc | 2104 void TurboAssembler::Pinsrq(XMMRegister dst, XMMRegister src1, Register src2, in CallRecordWriteStub() argument
1529 MovePair(Register dst0, Register src0, Register dst1, Register src1) CallRecordWriteStub() argument
2110 Pinsrq(XMMRegister dst, XMMRegister src1, Operand src2, uint8_t imm8, uint32_t* load_pc_offset) CallRecordWriteStub() argument
[all...] |
| /third_party/node/deps/v8/src/execution/arm64/ |
| H A D | simulator-logic-arm64.cc | 584 cmp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, Condition cond) cmp() argument
624 cmp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, int imm, Condition cond) cmp() argument
632 cmptst(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) cmptst() argument
644 add(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) add() argument
673 addp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) addp() argument
683 mla(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) mla() argument
692 mls(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) mls() argument
701 mul(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) mul() argument
711 mul(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) mul() argument
719 mla(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) mla() argument
727 mls(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) mls() argument
735 smull(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) smull() argument
744 smull2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) smull2() argument
753 umull(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) umull() argument
762 umull2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) umull2() argument
771 smlal(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) smlal() argument
780 smlal2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) smlal2() argument
789 umlal(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) umlal() argument
798 umlal2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) umlal2() argument
807 smlsl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) smlsl() argument
816 smlsl2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) smlsl2() argument
825 umlsl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) umlsl() argument
834 umlsl2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) umlsl2() argument
843 sqdmull(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) sqdmull() argument
852 sqdmull2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) sqdmull2() argument
861 sqdmlal(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) sqdmlal() argument
870 sqdmlal2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) sqdmlal2() argument
879 sqdmlsl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) sqdmlsl() argument
888 sqdmlsl2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) sqdmlsl2() argument
897 sqdmulh(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) sqdmulh() argument
905 sqrdmulh(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) sqrdmulh() argument
924 pmul(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) pmul() argument
935 pmull(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) pmull() argument
948 pmull2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) pmull2() argument
962 sub(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) sub() argument
991 and_(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) and_() argument
1001 orr(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) orr() argument
1011 orn(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) orn() argument
1021 eor(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) eor() argument
1031 bic(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) bic() argument
1052 bif(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) bif() argument
1066 bit(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) bit() argument
1080 bsl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) bsl() argument
1094 SMinMax(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, bool max) SMinMax() argument
1112 smax(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) smax() argument
1118 smin(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) smin() argument
1124 SMinMaxP(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, bool max) SMinMaxP() argument
1149 smaxp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) smaxp() argument
1155 sminp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) sminp() argument
1244 UMinMax(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, bool max) UMinMax() argument
1262 umax(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) umax() argument
1268 umin(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) umin() argument
1274 UMinMaxP(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, bool max) UMinMaxP() argument
1299 umaxp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) umaxp() argument
1305 uminp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) uminp() argument
1544 sshl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) sshl() argument
1603 ushl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) ushl() argument
1829 AbsDiff(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, bool issigned) AbsDiff() argument
1847 saba(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) saba() argument
1857 uaba(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) uaba() argument
1976 ext(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) ext() argument
2321 uaddl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) uaddl() argument
2331 uaddl2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) uaddl2() argument
2341 uaddw(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) uaddw() argument
2350 uaddw2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) uaddw2() argument
2359 saddl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) saddl() argument
2369 saddl2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) saddl2() argument
2379 saddw(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) saddw() argument
2388 saddw2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) saddw2() argument
2397 usubl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) usubl() argument
2407 usubl2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) usubl2() argument
2417 usubw(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) usubw() argument
2426 usubw2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) usubw2() argument
2435 ssubl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) ssubl() argument
2445 ssubl2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) ssubl2() argument
2455 ssubw(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) ssubw() argument
2464 ssubw2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) ssubw2() argument
2473 uabal(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) uabal() argument
2483 uabal2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) uabal2() argument
2493 sabal(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) sabal() argument
2503 sabal2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) sabal2() argument
2513 uabdl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) uabdl() argument
2523 uabdl2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) uabdl2() argument
2533 sabdl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) sabdl() argument
2543 sabdl2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) sabdl2() argument
2553 umull(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) umull() argument
2563 umull2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) umull2() argument
2573 smull(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) smull() argument
2583 smull2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) smull2() argument
2593 umlsl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) umlsl() argument
2603 umlsl2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) umlsl2() argument
2613 smlsl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) smlsl() argument
2623 smlsl2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) smlsl2() argument
2633 umlal(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) umlal() argument
2643 umlal2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) umlal2() argument
2653 smlal(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) smlal() argument
2663 smlal2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) smlal2() argument
2673 sqdmlal(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) sqdmlal() argument
2681 sqdmlal2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) sqdmlal2() argument
2689 sqdmlsl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) sqdmlsl() argument
2697 sqdmlsl2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) sqdmlsl2() argument
2705 sqdmull(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) sqdmull() argument
2713 sqdmull2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) sqdmull2() argument
2721 sqrdmulh(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, bool round) sqrdmulh() argument
2748 sqdmulh(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) sqdmulh() argument
2754 addhn(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) addhn() argument
2758 add(VectorFormatDoubleWidth(vform), temp, src1, src2); addhn() local
2763 addhn2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) addhn2() argument
2772 raddhn(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) raddhn() argument
2776 add(VectorFormatDoubleWidth(vform), temp, src1, src2); raddhn() local
2781 raddhn2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) raddhn2() argument
2790 subhn(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) subhn() argument
2794 sub(VectorFormatDoubleWidth(vform), temp, src1, src2); subhn() local
2799 subhn2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) subhn2() argument
2808 rsubhn(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) rsubhn() argument
2812 sub(VectorFormatDoubleWidth(vform), temp, src1, src2); rsubhn() local
2817 rsubhn2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) rsubhn2() argument
2826 trn1(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) trn1() argument
2841 trn2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) trn2() argument
2856 zip1(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) zip1() argument
2871 zip2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) zip2() argument
2886 uzp1(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) uzp1() argument
2903 uzp2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) uzp2() argument
3277 fnmul(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) fnmul() argument
3286 frecps(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) frecps() argument
3299 frecps(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) frecps() argument
3312 frsqrts(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) frsqrts() argument
3384 frsqrts(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) frsqrts() argument
3397 fcmp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, Condition cond) fcmp() argument
3432 fcmp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, Condition cond) fcmp() argument
3460 fabscmp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, Condition cond) fabscmp() argument
3478 fmla(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) fmla() argument
3492 fmla(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) fmla() argument
3505 fmls(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) fmls() argument
3519 fmls(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) fmls() argument
3579 fabd(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) fabd() argument
3665 fmul(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) fmul() argument
3681 fmla(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) fmla() argument
3697 fmls(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) fmls() argument
3713 fmulx(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) fmulx() argument
[all...] |
| /third_party/node/deps/v8/src/execution/s390/ |
| H A D | simulator-s390.cc | 3288 VectorBinaryOp(Simulator* sim, int dst, int src1, int src2, Operation op) VectorBinaryOp() argument
3434 VectorSum(Simulator* sim, int dst, int src1, int src2) VectorSum() argument
3528 VectorPack(Simulator* sim, int dst, int src1, int src2, bool saturate, const D& max = 0, const D& min = 0) VectorPack() argument
4189 int64_t src1 = get_simd_register_by_lane<int64_t>(r1, 0); EVALUATE() local
4400 FP_Type src1 = sim->get_fpr<FP_Type>(lhs); FPMinMaxForEachLane() local
4406 FP_Type src1 = sim->get_simd_register_by_lane<FP_Type>(lhs, i); FPMinMaxForEachLane() local
4446 VectorFPCompare(Simulator* sim, int dst, int src1, int src2, int m6, Operation op) VectorFPCompare() argument
[all...] |
| /third_party/node/deps/v8/src/execution/riscv64/ |
| H A D | simulator-riscv64.cc | 3493 static inline bool is_invalid_fmul(T src1, T src2) { in is_invalid_fmul() argument
3499 static inline bool is_invalid_fadd(T src1, T src2) { in is_invalid_fadd() argument
3505 static inline bool is_invalid_fsub(T src1, T src2) { in is_invalid_fsub() argument
3511 static inline bool is_invalid_fdiv(T src1, argument
3516 is_invalid_fsqrt(T src1) is_invalid_fsqrt() argument
[all...] |
| H A D | simulator-riscv64.h | 755 inline T CanonicalizeFPUOpFMA(Func fn, T dst, T src1, T src2) { in CanonicalizeFPUOpFMA() argument
772 T src1 = std::is_same<float, T>::value ? frs1() : drs1(); in CanonicalizeFPUOp3() local
790 T src1 = std::is_same<float, T>::value ? frs1() : drs1(); in CanonicalizeFPUOp2() local
806 T src1 = std::is_same<float, T>::value ? frs1() : drs1(); CanonicalizeFPUOp1() local
[all...] |
| /third_party/node/deps/v8/src/wasm/baseline/ia32/ |
| H A D | liftoff-assembler-ia32.h | 1862 Register src1 = src.high_gp() == dst.low_gp() ? src.high_gp() : src.low_gp(); in emit_i64_popcnt() local
[all...] |
| /third_party/node/deps/v8/src/wasm/baseline/arm/ |
| H A D | liftoff-assembler-arm.h | 1853 Register src1 = src.high_gp() == dst.low_gp() ? src.high_gp() : src.low_gp(); in emit_i64_popcnt() local
2475 emit_f64x2_replace_lane(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2, uint8_t imm_lane_idx) emit_f64x2_replace_lane() argument
2659 emit_f32x4_replace_lane(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2, uint8_t imm_lane_idx) emit_f32x4_replace_lane() argument
2845 emit_i64x2_replace_lane(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2, uint8_t imm_lane_idx) emit_i64x2_replace_lane() argument
2964 emit_i64x2_extmul_low_i32x4_s(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2) emit_i64x2_extmul_low_i32x4_s() argument
2971 emit_i64x2_extmul_low_i32x4_u(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2) emit_i64x2_extmul_low_i32x4_u() argument
2978 emit_i64x2_extmul_high_i32x4_s(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2) emit_i64x2_extmul_high_i32x4_s() argument
2985 emit_i64x2_extmul_high_i32x4_u(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2) emit_i64x2_extmul_high_i32x4_u() argument
3029 emit_i32x4_replace_lane(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2, uint8_t imm_lane_idx) emit_i32x4_replace_lane() argument
[all...] |
| /third_party/node/deps/v8/src/wasm/baseline/arm64/ |
| H A D | liftoff-assembler-arm64.h | 1789 emit_f64x2_replace_lane(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2, uint8_t imm_lane_idx) emit_f64x2_replace_lane() argument
1930 emit_f32x4_replace_lane(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2, uint8_t imm_lane_idx) emit_f32x4_replace_lane() argument
2054 emit_i64x2_replace_lane(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2, uint8_t imm_lane_idx) emit_i64x2_replace_lane() argument
2145 emit_i64x2_extmul_low_i32x4_s(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2) emit_i64x2_extmul_low_i32x4_s() argument
2151 emit_i64x2_extmul_low_i32x4_u(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2) emit_i64x2_extmul_low_i32x4_u() argument
2157 emit_i64x2_extmul_high_i32x4_s(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2) emit_i64x2_extmul_high_i32x4_s() argument
2163 emit_i64x2_extmul_high_i32x4_u(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2) emit_i64x2_extmul_high_i32x4_u() argument
2205 emit_i32x4_replace_lane(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2, uint8_t imm_lane_idx) emit_i32x4_replace_lane() argument
2340 emit_i32x4_extmul_low_i16x8_s(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2) emit_i32x4_extmul_low_i16x8_s() argument
2346 emit_i32x4_extmul_low_i16x8_u(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2) emit_i32x4_extmul_low_i16x8_u() argument
2352 emit_i32x4_extmul_high_i16x8_s(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2) emit_i32x4_extmul_high_i16x8_s() argument
2358 emit_i32x4_extmul_high_i16x8_u(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2) emit_i32x4_extmul_high_i16x8_u() argument
2381 emit_i16x8_replace_lane(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2, uint8_t imm_lane_idx) emit_i16x8_replace_lane() argument
2524 VRegister src1 = lhs.fp(); emit_i8x16_shuffle() local
2582 emit_i8x16_replace_lane(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2, uint8_t imm_lane_idx) emit_i8x16_replace_lane() argument
[all...] |
| /third_party/mesa3d/src/gallium/frontends/nine/ |
| H A D | nine_shader.c | 1659 struct ureg_src src1 = tx_src_param(tx, &tx->insn.src[1]); in DECL_SPECIAL() local
1680 struct ureg_src src1 = tx_src_param(tx, &tx->insn.src[1]); in DECL_SPECIAL() local
826 TEX_if_fetch4(struct shader_translator *tx, struct ureg_dst dst, unsigned target, struct ureg_src src0, struct ureg_src src1, INT idx) TEX_if_fetch4() argument
871 TEX_with_ps1x_projection(struct shader_translator *tx, struct ureg_dst dst, unsigned target, struct ureg_src src0, struct ureg_src src1, INT idx) TEX_with_ps1x_projection() argument
2906 struct ureg_src src1 = tx_src_param(tx, &tx->insn.src[1]); DECL_SPECIAL() local
[all...] |
| /third_party/mesa3d/src/gallium/auxiliary/tgsi/ |
| H A D | tgsi_exec.c | 129 micro_cmp(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1, const union tgsi_exec_channel *src2) micro_cmp() argument
391 micro_dldexp(union tgsi_double_channel *dst, const union tgsi_double_channel *src0, union tgsi_exec_channel *src1) micro_dldexp() argument
510 micro_lrp(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1, const union tgsi_exec_channel *src2) micro_lrp() argument
522 micro_mad(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1, const union tgsi_exec_channel *src2) micro_mad() argument
596 micro_seq(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) micro_seq() argument
607 micro_sge(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) micro_sge() argument
638 micro_sgt(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) micro_sgt() argument
659 micro_sle(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) micro_sle() argument
670 micro_slt(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) micro_slt() argument
681 micro_sne(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) micro_sne() argument
902 micro_u64shl(union tgsi_double_channel *dst, const union tgsi_double_channel *src0, union tgsi_exec_channel *src1) micro_u64shl() argument
918 micro_i64shr(union tgsi_double_channel *dst, const union tgsi_double_channel *src0, union tgsi_exec_channel *src1) micro_i64shr() argument
934 micro_u64shr(union tgsi_double_channel *dst, const union tgsi_double_channel *src0, union tgsi_exec_channel *src1) micro_u64shr() argument
1275 micro_add(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) micro_add() argument
1298 micro_lt( union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1, const union tgsi_exec_channel *src2, const union tgsi_exec_channel *src3 ) micro_lt() argument
1312 micro_max(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) micro_max() argument
1323 micro_min(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) micro_min() argument
1334 micro_mul(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) micro_mul() argument
1368 micro_ldexp(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) micro_ldexp() argument
1379 micro_sub(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) micro_sub() argument
3135 micro_ucmp(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1, const union tgsi_exec_channel *src2) micro_ucmp() argument
3541 union tgsi_exec_channel src1; exec_dldexp() local
3587 union tgsi_exec_channel src1; exec_arg0_64_arg1_32() local
4303 micro_shl(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) micro_shl() argument
4319 micro_and(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) micro_and() argument
4330 micro_or(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) micro_or() argument
4341 micro_xor(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) micro_xor() argument
4352 micro_mod(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) micro_mod() argument
4373 micro_fseq(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) micro_fseq() argument
4384 micro_fsge(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) micro_fsge() argument
4395 micro_fslt(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) micro_fslt() argument
4406 micro_fsne(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) micro_fsne() argument
4417 micro_idiv(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) micro_idiv() argument
4428 micro_imax(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) micro_imax() argument
4439 micro_imin(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) micro_imin() argument
4450 micro_isge(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) micro_isge() argument
4461 micro_ishr(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) micro_ishr() argument
4477 micro_islt(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) micro_islt() argument
4508 micro_uadd(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) micro_uadd() argument
4519 micro_udiv(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) micro_udiv() argument
4530 micro_umad(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1, const union tgsi_exec_channel *src2) micro_umad() argument
4542 micro_umax(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) micro_umax() argument
4553 micro_umin(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) micro_umin() argument
4564 micro_umod(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) micro_umod() argument
4575 micro_umul(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) micro_umul() argument
4586 micro_imul_hi(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) micro_imul_hi() argument
4599 micro_umul_hi(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) micro_umul_hi() argument
4612 micro_useq(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) micro_useq() argument
4623 micro_usge(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) micro_usge() argument
4634 micro_ushr(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) micro_ushr() argument
4650 micro_uslt(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) micro_uslt() argument
4661 micro_usne(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) micro_usne() argument
4685 micro_ibfe(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1, const union tgsi_exec_channel *src2) micro_ibfe() argument
4712 micro_ubfe(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1, const union tgsi_exec_channel *src2) micro_ubfe() argument
4739 micro_bfi(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1, const union tgsi_exec_channel *src2, const union tgsi_exec_channel *src3) micro_bfi() argument
[all...] |
| /third_party/mesa3d/src/gallium/auxiliary/nir/ |
| H A D | nir_to_tgsi.c | 133 ntt_insn(struct ntt_compile *c, enum tgsi_opcode opcode, struct ureg_dst dst, struct ureg_src src0, struct ureg_src src1, struct ureg_src src2, struct ureg_src src3) ntt_insn() argument
1295 ntt_emit_scalar(struct ntt_compile *c, unsigned tgsi_op, struct ureg_dst dst, struct ureg_src src0, struct ureg_src src1) ntt_emit_scalar() argument
[all...] |
| /third_party/pcre2/pcre2/src/sljit/ |
| H A D | sljitNativeMIPS_common.c | 1462 emit_single_op(struct sljit_compiler *compiler, sljit_s32 op, sljit_s32 flags, sljit_s32 dst, sljit_s32 src1, sljit_sw src2) emit_single_op() argument
2018 emit_op(struct sljit_compiler *compiler, sljit_s32 op, sljit_s32 flags, sljit_s32 dst, sljit_sw dstw, sljit_s32 src1, sljit_sw src1w, sljit_s32 src2, sljit_sw src2w) emit_op() argument
2313 sljit_emit_op2(struct sljit_compiler *compiler, sljit_s32 op, sljit_s32 dst, sljit_sw dstw, sljit_s32 src1, sljit_sw src1w, sljit_s32 src2, sljit_sw src2w) sljit_emit_op2() argument
2382 sljit_emit_op2u(struct sljit_compiler *compiler, sljit_s32 op, sljit_s32 src1, sljit_sw src1w, sljit_s32 src2, sljit_sw src2w) sljit_emit_op2u() argument
2401 sljit_emit_shift_into(struct sljit_compiler *compiler, sljit_s32 op, sljit_s32 src_dst, sljit_s32 src1, sljit_sw src1w, sljit_s32 src2, sljit_sw src2w) sljit_emit_shift_into() argument
2626 sljit_emit_fop1_cmp(struct sljit_compiler *compiler, sljit_s32 op, sljit_s32 src1, sljit_sw src1w, sljit_s32 src2, sljit_sw src2w) sljit_emit_fop1_cmp() argument
2731 sljit_emit_fop2(struct sljit_compiler *compiler, sljit_s32 op, sljit_s32 dst, sljit_sw dstw, sljit_s32 src1, sljit_sw src1w, sljit_s32 src2, sljit_sw src2w) sljit_emit_fop2() argument
3006 sljit_emit_cmp(struct sljit_compiler *compiler, sljit_s32 type, sljit_s32 src1, sljit_sw src1w, sljit_s32 src2, sljit_sw src2w) sljit_emit_cmp() argument
[all...] |
| /third_party/skia/third_party/externals/libwebp/src/dsp/ |
| H A D | enc_sse2.c | 300 const __m128i src1 = _mm_loadl_epi64((const __m128i*)&src[1 * BPS]); in FTransform_SSE2() local
345 const __m128i src1 = _mm_loadl_epi64((const __m128i*)&src[1 * BPS]); in FTransform2_SSE2() local
391 const __m128i src1 = _mm_loadl_epi64((__m128i*)&in[1 * 16]); in FTransformWHTRow_SSE2() local
|
| /third_party/mesa3d/src/amd/llvm/ |
| H A D | ac_nir_to_llvm.c | 150 emit_int_cmp(struct ac_llvm_context *ctx, LLVMIntPredicate pred, LLVMValueRef src0, LLVMValueRef src1) emit_int_cmp() argument
158 emit_float_cmp(struct ac_llvm_context *ctx, LLVMRealPredicate pred, LLVMValueRef src0, LLVMValueRef src1) emit_float_cmp() argument
207 emit_intrin_2f_param(struct ac_llvm_context *ctx, const char *intrin, LLVMTypeRef result_type, LLVMValueRef src0, LLVMValueRef src1) emit_intrin_2f_param() argument
223 emit_intrin_3f_param(struct ac_llvm_context *ctx, const char *intrin, LLVMTypeRef result_type, LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2) emit_intrin_3f_param() argument
240 emit_bcsel(struct ac_llvm_context *ctx, LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2) emit_bcsel() argument
263 emit_uint_carry(struct ac_llvm_context *ctx, const char *intrin, LLVMValueRef src0, LLVMValueRef src1) emit_uint_carry() argument
374 emit_umul_high(struct ac_llvm_context *ctx, LLVMValueRef src0, LLVMValueRef src1) emit_umul_high() argument
387 emit_imul_high(struct ac_llvm_context *ctx, LLVMValueRef src0, LLVMValueRef src1) emit_imul_high() argument
3185 LLVMValueRef src1 = get_src(ctx, instr->src[src_idx + 1]); visit_var_atomic() local
[all...] |
| H A D | ac_llvm_build.c | 4116 LLVMValueRef src0, src1; in _ac_build_dual_src_blend_swizzle() local
|
| /third_party/node/deps/v8/src/wasm/baseline/mips/ |
| H A D | liftoff-assembler-mips.h | 1228 Register src1 = src.high_gp() == dst.low_gp() ? src.high_gp() : src.low_gp(); in emit_i64_popcnt() local
1896 emit_i16x8_q15mulr_sat_s(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2) emit_i16x8_q15mulr_sat_s() argument
2077 emit_s128_select(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2, LiftoffRegister mask) emit_s128_select() argument
2852 emit_i8x16_replace_lane(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2, uint8_t imm_lane_idx) emit_i8x16_replace_lane() argument
2859 emit_i16x8_replace_lane(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2, uint8_t imm_lane_idx) emit_i16x8_replace_lane() argument
2866 emit_i32x4_replace_lane(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2, uint8_t imm_lane_idx) emit_i32x4_replace_lane() argument
2873 emit_i64x2_replace_lane(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2, uint8_t imm_lane_idx) emit_i64x2_replace_lane() argument
2880 emit_f32x4_replace_lane(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2, uint8_t imm_lane_idx) emit_f32x4_replace_lane() argument
2887 emit_f64x2_replace_lane(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2, uint8_t imm_lane_idx) emit_f64x2_replace_lane() argument
[all...] |
| /third_party/node/deps/v8/src/wasm/baseline/loong64/ |
| H A D | liftoff-assembler-loong64.h | 1881 emit_i16x8_q15mulr_sat_s(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2) emit_i16x8_q15mulr_sat_s() argument
2062 emit_s128_select(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2, LiftoffRegister mask) emit_s128_select() argument
2825 emit_i8x16_replace_lane(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2, uint8_t imm_lane_idx) emit_i8x16_replace_lane() argument
2832 emit_i16x8_replace_lane(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2, uint8_t imm_lane_idx) emit_i16x8_replace_lane() argument
2839 emit_i32x4_replace_lane(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2, uint8_t imm_lane_idx) emit_i32x4_replace_lane() argument
2846 emit_i64x2_replace_lane(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2, uint8_t imm_lane_idx) emit_i64x2_replace_lane() argument
2853 emit_f32x4_replace_lane(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2, uint8_t imm_lane_idx) emit_f32x4_replace_lane() argument
2860 emit_f64x2_replace_lane(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2, uint8_t imm_lane_idx) emit_f64x2_replace_lane() argument
[all...] |
| /third_party/node/deps/v8/src/codegen/s390/ |
| H A D | macro-assembler-s390.cc | 2278 void TurboAssembler::MovToFloatParameters(DoubleRegister src1, in CallRecordWriteStub() argument
2483 void TurboAssembler::MulS32(Register dst, const MemOperand& src1) { in CallRecordWriteStub() argument
2493 void TurboAssembler::MulS32(Register dst, Register src1) { ms in CallRecordWriteStub() argument
2495 MulS32(Register dst, const Operand& src1) CallRecordWriteStub() argument
2506 MulHighS32(Register dst, Register src1, const MemOperand& src2) CallRecordWriteStub() argument
2511 MulHighS32(Register dst, Register src1, Register src2) CallRecordWriteStub() argument
2518 MulHighS32(Register dst, Register src1, const Operand& src2) CallRecordWriteStub() argument
2532 MulHighU32(Register dst, Register src1, const MemOperand& src2) CallRecordWriteStub() argument
2537 MulHighU32(Register dst, Register src1, Register src2) CallRecordWriteStub() argument
2541 MulHighU32(Register dst, Register src1, const Operand& src2) CallRecordWriteStub() argument
2558 Mul32WithOverflowIfCCUnequal(Register dst, Register src1, const MemOperand& src2) CallRecordWriteStub() argument
2566 Mul32WithOverflowIfCCUnequal(Register dst, Register src1, Register src2) CallRecordWriteStub() argument
2574 Mul32WithOverflowIfCCUnequal(Register dst, Register src1, const Operand& src2) CallRecordWriteStub() argument
2588 DivS32(Register dst, Register src1, const MemOperand& src2) CallRecordWriteStub() argument
2593 DivS32(Register dst, Register src1, Register src2) CallRecordWriteStub() argument
2607 DivU32(Register dst, Register src1, const MemOperand& src2) CallRecordWriteStub() argument
2612 DivU32(Register dst, Register src1, Register src2) CallRecordWriteStub() argument
2625 DivS64(Register dst, Register src1, const MemOperand& src2) CallRecordWriteStub() argument
2630 DivS64(Register dst, Register src1, Register src2) CallRecordWriteStub() argument
2644 DivU64(Register dst, Register src1, const MemOperand& src2) CallRecordWriteStub() argument
2649 DivU64(Register dst, Register src1, Register src2) CallRecordWriteStub() argument
2662 ModS32(Register dst, Register src1, const MemOperand& src2) CallRecordWriteStub() argument
2667 ModS32(Register dst, Register src1, Register src2) CallRecordWriteStub() argument
2681 ModU32(Register dst, Register src1, const MemOperand& src2) CallRecordWriteStub() argument
2686 ModU32(Register dst, Register src1, Register src2) CallRecordWriteStub() argument
2699 ModS64(Register dst, Register src1, const MemOperand& src2) CallRecordWriteStub() argument
2704 ModS64(Register dst, Register src1, Register src2) CallRecordWriteStub() argument
2718 ModU64(Register dst, Register src1, const MemOperand& src2) CallRecordWriteStub() argument
2723 ModU64(Register dst, Register src1, Register src2) CallRecordWriteStub() argument
2809 AddS32(Register dst, Register src1, Register src2) CallRecordWriteStub() argument
2826 AddS64(Register dst, Register src1, Register src2) CallRecordWriteStub() argument
2878 AddU32(Register dst, Register src1, Register src2) CallRecordWriteStub() argument
2903 AddU64(Register dst, Register src1, Register src2) CallRecordWriteStub() argument
2942 SubU32(Register dst, Register src1, Register src2) CallRecordWriteStub() argument
2993 SubS32(Register dst, Register src1, Register src2) CallRecordWriteStub() argument
3013 SubS64(Register dst, Register src1, Register src2) CallRecordWriteStub() argument
3107 And(Register dst, Register src1, Register src2) CallRecordWriteStub() argument
3124 AndP(Register dst, Register src1, Register src2) CallRecordWriteStub() argument
3230 Or(Register dst, Register src1, Register src2) CallRecordWriteStub() argument
3247 OrP(Register dst, Register src1, Register src2) CallRecordWriteStub() argument
3318 Xor(Register dst, Register src1, Register src2) CallRecordWriteStub() argument
3335 XorP(Register dst, Register src1, Register src2) CallRecordWriteStub() argument
3433 CmpS32(Register src1, Register src2) CallRecordWriteStub() argument
3436 CmpS64(Register src1, Register src2) CallRecordWriteStub() argument
3584 CmpSmiLiteral(Register src1, Smi smi, Register scratch) CallRecordWriteStub() argument
3656 StoreMultipleP(Register src1, Register src2, const MemOperand& mem) CallRecordWriteStub() argument
3681 StoreMultipleW(Register src1, Register src2, const MemOperand& mem) CallRecordWriteStub() argument
5185 F64x2ReplaceLane(Simd128Register dst, Simd128Register src1, DoubleRegister src2, uint8_t imm_lane_idx, Register scratch) CallRecordWriteStub() argument
5195 F32x4ReplaceLane(Simd128Register dst, Simd128Register src1, DoubleRegister src2, uint8_t imm_lane_idx, Register scratch) CallRecordWriteStub() argument
5205 I64x2ReplaceLane(Simd128Register dst, Simd128Register src1, Register src2, uint8_t imm_lane_idx, Register) CallRecordWriteStub() argument
5214 I32x4ReplaceLane(Simd128Register dst, Simd128Register src1, Register src2, uint8_t imm_lane_idx, Register) CallRecordWriteStub() argument
5223 I16x8ReplaceLane(Simd128Register dst, Simd128Register src1, Register src2, uint8_t imm_lane_idx, Register) CallRecordWriteStub() argument
5232 I8x16ReplaceLane(Simd128Register dst, Simd128Register src1, Register src2, uint8_t imm_lane_idx, Register) CallRecordWriteStub() argument
5253 S128Select(Simd128Register dst, Simd128Register src1, Simd128Register src2, Simd128Register mask) CallRecordWriteStub() argument
5475 I64x2Mul(Simd128Register dst, Simd128Register src1, Simd128Register src2, Register scratch1, Register scratch2, Register scratch3) CallRecordWriteStub() argument
5490 F64x2Ne(Simd128Register dst, Simd128Register src1, Simd128Register src2) CallRecordWriteStub() argument
5496 F64x2Lt(Simd128Register dst, Simd128Register src1, Simd128Register src2) CallRecordWriteStub() argument
5501 F64x2Le(Simd128Register dst, Simd128Register src1, Simd128Register src2) CallRecordWriteStub() argument
5506 F32x4Ne(Simd128Register dst, Simd128Register src1, Simd128Register src2) CallRecordWriteStub() argument
5512 F32x4Lt(Simd128Register dst, Simd128Register src1, Simd128Register src2) CallRecordWriteStub() argument
5517 F32x4Le(Simd128Register dst, Simd128Register src1, Simd128Register src2) CallRecordWriteStub() argument
5522 I64x2Ne(Simd128Register dst, Simd128Register src1, Simd128Register src2) CallRecordWriteStub() argument
5528 I64x2GeS(Simd128Register dst, Simd128Register src1, Simd128Register src2) CallRecordWriteStub() argument
5535 I32x4Ne(Simd128Register dst, Simd128Register src1, Simd128Register src2) CallRecordWriteStub() argument
5541 I32x4GeS(Simd128Register dst, Simd128Register src1, Simd128Register src2) CallRecordWriteStub() argument
5548 I32x4GeU(Simd128Register dst, Simd128Register src1, Simd128Register src2, Simd128Register scratch) CallRecordWriteStub() argument
5555 I16x8Ne(Simd128Register dst, Simd128Register src1, Simd128Register src2) CallRecordWriteStub() argument
5561 I16x8GeS(Simd128Register dst, Simd128Register src1, Simd128Register src2) CallRecordWriteStub() argument
5568 I16x8GeU(Simd128Register dst, Simd128Register src1, Simd128Register src2, Simd128Register scratch) CallRecordWriteStub() argument
5575 I8x16Ne(Simd128Register dst, Simd128Register src1, Simd128Register src2) CallRecordWriteStub() argument
5581 I8x16GeS(Simd128Register dst, Simd128Register src1, Simd128Register src2) CallRecordWriteStub() argument
5588 I8x16GeU(Simd128Register dst, Simd128Register src1, Simd128Register src2, Simd128Register scratch) CallRecordWriteStub() argument
5715 I16x8SConvertI32x4(Simd128Register dst, Simd128Register src1, Simd128Register src2) CallRecordWriteStub() argument
5721 I8x16SConvertI16x8(Simd128Register dst, Simd128Register src1, Simd128Register src2) CallRecordWriteStub() argument
5733 I16x8UConvertI32x4(Simd128Register dst, Simd128Register src1, Simd128Register src2, Simd128Register scratch) CallRecordWriteStub() argument
5742 I8x16UConvertI16x8(Simd128Register dst, Simd128Register src1, Simd128Register src2, Simd128Register scratch) CallRecordWriteStub() argument
5764 I16x8AddSatS(Simd128Register dst, Simd128Register src1, Simd128Register src2, Simd128Register scratch1, Simd128Register scratch2) CallRecordWriteStub() argument
5772 I16x8SubSatS(Simd128Register dst, Simd128Register src1, Simd128Register src2, Simd128Register scratch1, Simd128Register scratch2) CallRecordWriteStub() argument
5780 I16x8AddSatU(Simd128Register dst, Simd128Register src1, Simd128Register src2, Simd128Register scratch1, Simd128Register scratch2) CallRecordWriteStub() argument
5788 I16x8SubSatU(Simd128Register dst, Simd128Register src1, Simd128Register src2, Simd128Register scratch1, Simd128Register scratch2) CallRecordWriteStub() argument
5802 I8x16AddSatS(Simd128Register dst, Simd128Register src1, Simd128Register src2, Simd128Register scratch1, Simd128Register scratch2) CallRecordWriteStub() argument
5810 I8x16SubSatS(Simd128Register dst, Simd128Register src1, Simd128Register src2, Simd128Register scratch1, Simd128Register scratch2) CallRecordWriteStub() argument
5818 I8x16AddSatU(Simd128Register dst, Simd128Register src1, Simd128Register src2, Simd128Register scratch1, Simd128Register scratch2) CallRecordWriteStub() argument
5826 I8x16SubSatU(Simd128Register dst, Simd128Register src1, Simd128Register src2, Simd128Register scratch1, Simd128Register scratch2) CallRecordWriteStub() argument
5942 I8x16Swizzle(Simd128Register dst, Simd128Register src1, Simd128Register src2, Register scratch1, Register scratch2, Simd128Register scratch3, Simd128Register scratch4) CallRecordWriteStub() argument
5962 I8x16Shuffle(Simd128Register dst, Simd128Register src1, Simd128Register src2, uint64_t high, uint64_t low, Register scratch1, Register scratch2, Simd128Register scratch3) CallRecordWriteStub() argument
5972 I32x4DotI16x8S(Simd128Register dst, Simd128Register src1, Simd128Register src2, Simd128Register scratch) CallRecordWriteStub() argument
5990 I16x8Q15MulRSatS(Simd128Register dst, Simd128Register src1, Simd128Register src2, Simd128Register scratch1, Simd128Register scratch2, Simd128Register scratch3) CallRecordWriteStub() argument
[all...] |
| /third_party/node/deps/v8/src/codegen/mips64/ |
| H A D | assembler-mips64.cc | 3133 void Assembler::fcmp(FPURegister src1, const double src2, FPUCondition cond) { in fcmp() argument
|
| /third_party/node/deps/v8/src/codegen/mips/ |
| H A D | macro-assembler-mips.cc | 4277 void TurboAssembler::MovToFloatParameters(DoubleRegister src1, in CallRecordWriteStub() argument
5146 void TurboAssembler::Float32Max(FPURegister dst, FPURegister src1, in CallRecordWriteStub() argument
106 LoadRoot(Register destination, RootIndex index, Condition cond, Register src1, const Operand& src2) LoadRoot() argument
5191 Float32MaxOutOfLine(FPURegister dst, FPURegister src1, FPURegister src2) CallRecordWriteStub() argument
5196 Float32Min(FPURegister dst, FPURegister src1, FPURegister src2, Label* out_of_line) CallRecordWriteStub() argument
5241 Float32MinOutOfLine(FPURegister dst, FPURegister src1, FPURegister src2) CallRecordWriteStub() argument
5246 Float64Max(DoubleRegister dst, DoubleRegister src1, DoubleRegister src2, Label* out_of_line) CallRecordWriteStub() argument
5291 Float64MaxOutOfLine(DoubleRegister dst, DoubleRegister src1, DoubleRegister src2) CallRecordWriteStub() argument
5297 Float64Min(DoubleRegister dst, DoubleRegister src1, DoubleRegister src2, Label* out_of_line) CallRecordWriteStub() argument
5342 Float64MinOutOfLine(DoubleRegister dst, DoubleRegister src1, DoubleRegister src2) CallRecordWriteStub() argument
[all...] |
| H A D | assembler-mips.cc | 2927 void Assembler::fcmp(FPURegister src1, const double src2, FPUCondition cond) { in fcmp() argument
|