| /third_party/mesa3d/src/freedreno/ir3/ |
| H A D | ir3.h | 2331 ir3_SAM(struct ir3_block *block, opc_t opc, type_t type, unsigned wrmask, unsigned flags, struct ir3_instruction *samp_tex, struct ir3_instruction *src0, struct ir3_instruction *src1) ir3_SAM() argument
|
| /third_party/mesa3d/src/compiler/spirv/ |
| H A D | spirv_to_nir.c | 3891 vtn_vector_shuffle(struct vtn_builder *b, unsigned num_components, nir_ssa_def *src0, nir_ssa_def *src1, const uint32_t *indices) vtn_vector_shuffle() argument 5405 vtn_nir_select(struct vtn_builder *b, struct vtn_ssa_value *src0, struct vtn_ssa_value *src1, struct vtn_ssa_value *src2) vtn_nir_select() argument 5705 ray_query_load_intrinsic_create(struct vtn_builder *b, SpvOp opcode, const uint32_t *w, nir_ssa_def *src0, nir_ssa_def *src1) ray_query_load_intrinsic_create() argument [all...] |
| /third_party/mesa3d/src/broadcom/compiler/ |
| H A D | nir_to_vir.c | 1163 struct qreg src1; in ntq_emit_comparison() local [all...] |
| /third_party/mesa3d/src/gallium/drivers/zink/ |
| H A D | zink_compiler.c | 2837 nir_ssa_def *src1; in lower_sparse_instr() local
|
| /third_party/mesa3d/src/gallium/drivers/zink/nir_to_spirv/ |
| H A D | nir_to_spirv.c | 1704 emit_atomic(struct ntv_context *ctx, SpvId op, SpvId type, SpvId src0, SpvId src1, SpvId src2) in emit_atomic() argument 1721 emit_binop(struct ntv_context *ctx, SpvOp op, SpvId type, SpvId src0, SpvId src1) emit_binop() argument 1728 emit_triop(struct ntv_context *ctx, SpvOp op, SpvId type, SpvId src0, SpvId src1, SpvId src2) emit_triop() argument 1744 emit_builtin_binop(struct ntv_context *ctx, enum GLSLstd450 op, SpvId type, SpvId src0, SpvId src1) emit_builtin_binop() argument 1753 emit_builtin_triop(struct ntv_context *ctx, enum GLSLstd450 op, SpvId type, SpvId src0, SpvId src1, SpvId src2) emit_builtin_triop() argument 2623 SpvId src1 = 0; emit_interpolate() local [all...] |
| /third_party/node/deps/v8/src/wasm/baseline/ppc/ |
| H A D | liftoff-assembler-ppc.h | 1787 emit_f64x2_replace_lane(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2, uint8_t imm_lane_idx) emit_f64x2_replace_lane() argument 1899 emit_f32x4_replace_lane(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2, uint8_t imm_lane_idx) emit_f32x4_replace_lane() argument 1996 emit_i64x2_replace_lane(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2, uint8_t imm_lane_idx) emit_i64x2_replace_lane() argument 2060 emit_i64x2_extmul_low_i32x4_s(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2) emit_i64x2_extmul_low_i32x4_s() argument 2066 emit_i64x2_extmul_low_i32x4_u(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2) emit_i64x2_extmul_low_i32x4_u() argument 2072 emit_i64x2_extmul_high_i32x4_s(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2) emit_i64x2_extmul_high_i32x4_s() argument 2103 emit_i64x2_extmul_high_i32x4_u(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2) emit_i64x2_extmul_high_i32x4_u() argument 2120 emit_i32x4_replace_lane(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2, uint8_t imm_lane_idx) emit_i32x4_replace_lane() argument 2229 emit_i32x4_extmul_low_i16x8_s(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2) emit_i32x4_extmul_low_i16x8_s() argument 2235 emit_i32x4_extmul_low_i16x8_u(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2) emit_i32x4_extmul_low_i16x8_u() argument 2241 emit_i32x4_extmul_high_i16x8_s(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2) emit_i32x4_extmul_high_i16x8_s() argument 2247 emit_i32x4_extmul_high_i16x8_u(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2) emit_i32x4_extmul_high_i16x8_u() argument 2374 emit_i16x8_replace_lane(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2, uint8_t imm_lane_idx) emit_i16x8_replace_lane() argument 2397 emit_i16x8_extmul_low_i8x16_s(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2) emit_i16x8_extmul_low_i8x16_s() argument 2403 emit_i16x8_extmul_low_i8x16_u(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2) emit_i16x8_extmul_low_i8x16_u() argument 2409 emit_i16x8_extmul_high_i8x16_s(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2) emit_i16x8_extmul_high_i8x16_s() argument 2415 emit_i16x8_q15mulr_sat_s(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2) emit_i16x8_q15mulr_sat_s() argument 2421 emit_i16x8_extmul_high_i8x16_u(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2) emit_i16x8_extmul_high_i8x16_u() argument 2451 emit_i8x16_replace_lane(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2, uint8_t imm_lane_idx) emit_i8x16_replace_lane() argument 2725 emit_s128_select(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2, LiftoffRegister mask) emit_s128_select() argument [all...] |
| /third_party/mesa3d/src/gallium/drivers/llvmpipe/ |
| H A D | lp_state_fs.c | 2388 LLVMValueRef src1[4 * 4]; in generate_unswizzled_blend() local [all...] |
| /third_party/node/deps/v8/src/compiler/backend/arm64/ |
| H A D | instruction-selector-arm64.cc | 4177 InstructionOperand src0, src1; in VisitI8x16Shuffle() local 4115 ArrangeShuffleTable(Arm64OperandGenerator* g, Node* input0, Node* input1, InstructionOperand* src0, InstructionOperand* src1) ArrangeShuffleTable() argument
|
| /third_party/node/deps/v8/src/compiler/backend/riscv64/ |
| H A D | instruction-selector-riscv64.cc | 992 InstructionOperand src1 = g.TempSimd128Register(); in VisitI32x4ExtAddPairwiseI16x8S() local 1005 InstructionOperand src1 = g.TempSimd128Register(); in VisitI32x4ExtAddPairwiseI16x8U() local 1018 InstructionOperand src1 = g.TempSimd128Register(); in VisitI16x8ExtAddPairwiseI8x16S() local 1031 InstructionOperand src1 in VisitI16x8ExtAddPairwiseI8x16U() local [all...] |
| /third_party/node/deps/v8/src/codegen/mips64/ |
| H A D | macro-assembler-mips64.cc | 4803 void TurboAssembler::MovToFloatParameters(DoubleRegister src1, in CallRecordWriteStub() argument 103 LoadRoot(Register destination, RootIndex index, Condition cond, Register src1, const Operand& src2) LoadRoot() argument 5694 Float32Max(FPURegister dst, FPURegister src1, FPURegister src2, Label* out_of_line) CallRecordWriteStub() argument 5740 Float32MaxOutOfLine(FPURegister dst, FPURegister src1, FPURegister src2) CallRecordWriteStub() argument 5745 Float32Min(FPURegister dst, FPURegister src1, FPURegister src2, Label* out_of_line) CallRecordWriteStub() argument 5791 Float32MinOutOfLine(FPURegister dst, FPURegister src1, FPURegister src2) CallRecordWriteStub() argument 5796 Float64Max(FPURegister dst, FPURegister src1, FPURegister src2, Label* out_of_line) CallRecordWriteStub() argument 5841 Float64MaxOutOfLine(FPURegister dst, FPURegister src1, FPURegister src2) CallRecordWriteStub() argument 5846 Float64Min(FPURegister dst, FPURegister src1, FPURegister src2, Label* out_of_line) CallRecordWriteStub() argument 5891 Float64MinOutOfLine(FPURegister dst, FPURegister src1, FPURegister src2) CallRecordWriteStub() argument [all...] |
| /third_party/node/deps/v8/src/codegen/arm/ |
| H A D | macro-assembler-arm.cc | 542 void MacroAssembler::Mls(Register dst, Register src1, Register src2, in Mls() argument 556 void MacroAssembler::And(Register dst, Register src1, const Operand& src2, in And() argument 496 MovePair(Register dst0, Register src0, Register dst1, Register src1) MovePair() argument 575 Ubfx(Register dst, Register src1, int lsb, int width, Condition cond) Ubfx() argument 590 Sbfx(Register dst, Register src1, int lsb, int width, Condition cond) Sbfx() argument 869 VFPCompareAndSetFlags(const SwVfpRegister src1, const SwVfpRegister src2, const Condition cond) CallRecordWriteStub() argument 876 VFPCompareAndSetFlags(const SwVfpRegister src1, const float src2, const Condition cond) CallRecordWriteStub() argument 883 VFPCompareAndSetFlags(const DwVfpRegister src1, const DwVfpRegister src2, const Condition cond) CallRecordWriteStub() argument 890 VFPCompareAndSetFlags(const DwVfpRegister src1, const double src2, const Condition cond) CallRecordWriteStub() argument 897 VFPCompareAndLoadFlags(const SwVfpRegister src1, const SwVfpRegister src2, const Register fpscr_flags, const Condition cond) CallRecordWriteStub() argument 906 VFPCompareAndLoadFlags(const SwVfpRegister src1, const float src2, const Register fpscr_flags, const Condition cond) CallRecordWriteStub() argument 915 VFPCompareAndLoadFlags(const DwVfpRegister src1, const DwVfpRegister src2, const Register fpscr_flags, const Condition cond) CallRecordWriteStub() argument 924 VFPCompareAndLoadFlags(const DwVfpRegister src1, const double src2, const Register fpscr_flags, const Condition cond) CallRecordWriteStub() argument 2486 MovToFloatParameters(DwVfpRegister src1, DwVfpRegister src2) CallRecordWriteStub() argument 2672 I64x2Eq(QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2) CallRecordWriteStub() argument 2681 I64x2Ne(QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2) CallRecordWriteStub() argument 2691 I64x2GtS(QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2) CallRecordWriteStub() argument 2698 I64x2GeS(QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2) CallRecordWriteStub() argument [all...] |
| /third_party/node/deps/v8/src/codegen/arm64/ |
| H A D | macro-assembler-arm64.cc | 71 const CPURegister& src1 = registers.PopHighestIndex(); in PushCPURegList() local 1116 void TurboAssembler::Push(const CPURegister& src0, const CPURegister& src1, in Push() argument 1176 PushHelper(int count, int size, const CPURegister& src0, const CPURegister& src1, const CPURegister& src2, const CPURegister& src3) PushHelper() argument 1252 PokePair(const CPURegister& src1, const CPURegister& src2, int offset) PokePair() argument 1494 MovePair(Register dst0, Register src0, Register dst1, Register src1) MovePair() argument [all...] |
| /third_party/node/deps/v8/src/codegen/ppc/ |
| H A D | macro-assembler-ppc.cc | 2274 void TurboAssembler::MovToFloatParameters(DoubleRegister src1, in CallRecordWriteStub() argument 2997 void TurboAssembler::CmpS64(Register src1, Register src2, CRegister cr) { in CallRecordWriteStub() argument 3001 void TurboAssembler::CmpS64(Register src1, const Operand& src2, in CallRecordWriteStub() argument 3012 void TurboAssembler::CmpU64(Register src1, cons in CallRecordWriteStub() argument 3023 CmpU64(Register src1, Register src2, CRegister cr) CallRecordWriteStub() argument 3027 CmpS32(Register src1, const Operand& src2, Register scratch, CRegister cr) CallRecordWriteStub() argument 3038 CmpS32(Register src1, Register src2, CRegister cr) CallRecordWriteStub() argument 3042 CmpU32(Register src1, const Operand& src2, Register scratch, CRegister cr) CallRecordWriteStub() argument 3053 CmpU32(Register src1, Register src2, CRegister cr) CallRecordWriteStub() argument 3106 CmpSmiLiteral(Register src1, Smi smi, Register scratch, CRegister cr) CallRecordWriteStub() argument 3116 CmplSmiLiteral(Register src1, Smi smi, Register scratch, CRegister cr) CallRecordWriteStub() argument [all...] |
| H A D | assembler-ppc.cc | 798 void Assembler::addc(Register dst, Register src1, Register src2, OEBit o, in addc() argument 803 void Assembler::adde(Register dst, Register src1, Register src2, OEBit o, in adde() argument 808 void Assembler::addze(Register dst, Register src1, OEBit o, RCBit r) { in addze() argument 813 void Assembler::sub(Register dst, Register src1, Register src2, OEBit o, in sub() argument 818 void Assembler::subc(Register dst, Register src1, Register src2, OEBit o, in subc() argument 823 sube(Register dst, Register src1, Register src2, OEBit o, RCBit r) sube() argument 832 add(Register dst, Register src1, Register src2, OEBit o, RCBit r) add() argument 838 mullw(Register dst, Register src1, Register src2, OEBit o, RCBit r) mullw() argument 848 mulhw(Register dst, Register src1, Register src2, RCBit r) mulhw() argument 853 mulhwu(Register dst, Register src1, Register src2, RCBit r) mulhwu() argument 858 divw(Register dst, Register src1, Register src2, OEBit o, RCBit r) divw() argument 864 divwu(Register dst, Register src1, Register src2, OEBit o, RCBit r) divwu() argument 899 cmpi(Register src1, const Operand& src2, CRegister cr) cmpi() argument 912 cmpli(Register src1, const Operand& src2, CRegister cr) cmpli() argument 925 cmpwi(Register src1, const Operand& src2, CRegister cr) cmpwi() argument 942 cmplwi(Register src1, const Operand& src2, CRegister cr) cmplwi() argument 1128 mulld(Register dst, Register src1, Register src2, OEBit o, RCBit r) mulld() argument 1133 divd(Register dst, Register src1, Register src2, OEBit o, RCBit r) divd() argument 1138 divdu(Register dst, Register src1, Register src2, OEBit o, RCBit r) divdu() argument [all...] |
| /third_party/node/deps/v8/src/codegen/ia32/ |
| H A D | assembler-ia32.cc | 2865 void Assembler::vss(byte op, XMMRegister dst, XMMRegister src1, Operand src2) { in vss() argument 2869 void Assembler::vps(byte op, XMMRegister dst, XMMRegister src1, Operand src2) { in vps() argument 2873 void Assembler::vpd(byte op, XMMRegister dst, XMMRegister src1, Operand src2) { in vpd() argument 2877 void Assembler::vshufpd(XMMRegister dst, XMMRegister src1, Operand src2, in vshufpd() argument 2884 void Assembler::vmovhlps(XMMRegister dst, XMMRegister src1, XMMRegister src2) { in vmovhlps() argument 2888 vmovlhps(XMMRegister dst, XMMRegister src1, XMMRegister src2) vmovlhps() argument 2892 vmovlps(XMMRegister dst, XMMRegister src1, Operand src2) vmovlps() argument 2900 vmovhps(XMMRegister dst, XMMRegister src1, Operand src2) vmovhps() argument 2908 vcmpps(XMMRegister dst, XMMRegister src1, Operand src2, uint8_t cmp) vcmpps() argument 2914 vcmppd(XMMRegister dst, XMMRegister src1, Operand src2, uint8_t cmp) vcmppd() argument 2920 vshufps(XMMRegister dst, XMMRegister src1, Operand src2, byte imm8) vshufps() argument 2990 vblendvps(XMMRegister dst, XMMRegister src1, XMMRegister src2, XMMRegister mask) vblendvps() argument 2996 vblendvpd(XMMRegister dst, XMMRegister src1, XMMRegister src2, XMMRegister mask) vblendvpd() argument 3002 vpblendvb(XMMRegister dst, XMMRegister src1, XMMRegister src2, XMMRegister mask) vpblendvb() argument 3008 vpblendw(XMMRegister dst, XMMRegister src1, Operand src2, uint8_t mask) vpblendw() argument 3014 vpalignr(XMMRegister dst, XMMRegister src1, Operand src2, uint8_t mask) vpalignr() argument 3035 vinsertps(XMMRegister dst, XMMRegister src1, Operand src2, uint8_t offset) vinsertps() argument 3041 vpinsrb(XMMRegister dst, XMMRegister src1, Operand src2, uint8_t offset) vpinsrb() argument 3047 vpinsrw(XMMRegister dst, XMMRegister src1, Operand src2, uint8_t offset) vpinsrw() argument 3053 vpinsrd(XMMRegister dst, XMMRegister src1, Operand src2, uint8_t offset) vpinsrd() argument 3059 vroundsd(XMMRegister dst, XMMRegister src1, XMMRegister src2, RoundingMode mode) vroundsd() argument 3064 vroundss(XMMRegister dst, XMMRegister src1, XMMRegister src2, RoundingMode mode) vroundss() argument 3107 vpcmpgtq(XMMRegister dst, XMMRegister src1, XMMRegister src2) vpcmpgtq() argument 3205 vinstr(byte op, XMMRegister dst, XMMRegister src1, XMMRegister src2, SIMDPrefix pp, LeadingOpcode m, VexW w, CpuFeature feature) vinstr() argument 3211 vinstr(byte op, XMMRegister dst, XMMRegister src1, Operand src2, SIMDPrefix pp, LeadingOpcode m, VexW w, CpuFeature feature) vinstr() argument 3217 vinstr(byte op, XMMRegister dst, XMMRegister src1, XMMRegister src2, VectorLength l, SIMDPrefix pp, LeadingOpcode m, VexW w, CpuFeature feature) vinstr() argument 3227 vinstr(byte op, XMMRegister dst, XMMRegister src1, Operand src2, VectorLength l, SIMDPrefix pp, LeadingOpcode m, VexW w, CpuFeature feature) vinstr() argument [all...] |
| /third_party/node/deps/v8/src/codegen/loong64/ |
| H A D | macro-assembler-loong64.cc | 3814 void TurboAssembler::Float32Max(FPURegister dst, FPURegister src1, in CallRecordWriteStub() argument 3829 void TurboAssembler::Float32MaxOutOfLine(FPURegister dst, FPURegister src1, in CallRecordWriteStub() argument 3834 void TurboAssembler::Float32Min(FPURegister dst, FPURegister src1, in CallRecordWriteStub() argument 3849 Float32MinOutOfLine(FPURegister dst, FPURegister src1, FPURegister src2) CallRecordWriteStub() argument 3854 Float64Max(FPURegister dst, FPURegister src1, FPURegister src2, Label* out_of_line) CallRecordWriteStub() argument 3869 Float64MaxOutOfLine(FPURegister dst, FPURegister src1, FPURegister src2) CallRecordWriteStub() argument 3874 Float64Min(FPURegister dst, FPURegister src1, FPURegister src2, Label* out_of_line) CallRecordWriteStub() argument 3889 Float64MinOutOfLine(FPURegister dst, FPURegister src1, FPURegister src2) CallRecordWriteStub() argument [all...] |
| /third_party/node/deps/v8/src/codegen/x64/ |
| H A D | assembler-x64.cc | 3523 void Assembler::fma_instr(byte op, XMMRegister dst, XMMRegister src1, in fma_instr() argument 3533 void Assembler::fma_instr(byte op, XMMRegister dst, XMMRegister src1, in fma_instr() argument 3675 void Assembler::vmovlps(XMMRegister dst, XMMRegister src1, Operand src2) { in vmovlps() argument 3691 void Assembler::vmovhps(XMMRegister dst, XMMRegister src1, Operand src2) { in vmovhps() argument 3707 void Assembler::vinstr(byte op, XMMRegister dst, XMMRegister src1, in vinstr() argument 3718 vinstr(byte op, XMMRegister dst, XMMRegister src1, Operand src2, SIMDPrefix pp, LeadingOpcode m, VexW w, CpuFeature feature) vinstr() argument 3730 vinstr(byte op, Reg1 dst, Reg2 src1, Op src2, SIMDPrefix pp, LeadingOpcode m, VexW w, CpuFeature feature) vinstr() argument 3756 vps(byte op, XMMRegister dst, XMMRegister src1, XMMRegister src2) vps() argument 3765 vps(byte op, YMMRegister dst, YMMRegister src1, YMMRegister src2) vps() argument 3774 vps(byte op, XMMRegister dst, XMMRegister src1, Operand src2) vps() argument 3782 vps(byte op, YMMRegister dst, YMMRegister src1, Operand src2) vps() argument 3790 vps(byte op, XMMRegister dst, XMMRegister src1, XMMRegister src2, byte imm8) vps() argument 3800 vps(byte op, YMMRegister dst, YMMRegister src1, YMMRegister src2, byte imm8) vps() argument 3857 vss(byte op, XMMRegister dst, XMMRegister src1, XMMRegister src2) vss() argument 3866 vss(byte op, XMMRegister dst, XMMRegister src1, Operand src2) vss() argument [all...] |
| H A D | macro-assembler-x64.cc | 2104 void TurboAssembler::Pinsrq(XMMRegister dst, XMMRegister src1, Register src2, in CallRecordWriteStub() argument 1529 MovePair(Register dst0, Register src0, Register dst1, Register src1) CallRecordWriteStub() argument 2110 Pinsrq(XMMRegister dst, XMMRegister src1, Operand src2, uint8_t imm8, uint32_t* load_pc_offset) CallRecordWriteStub() argument [all...] |
| /third_party/node/deps/v8/src/execution/arm64/ |
| H A D | simulator-logic-arm64.cc | 584 cmp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, Condition cond) cmp() argument 624 cmp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, int imm, Condition cond) cmp() argument 632 cmptst(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) cmptst() argument 644 add(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) add() argument 673 addp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) addp() argument 683 mla(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) mla() argument 692 mls(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) mls() argument 701 mul(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) mul() argument 711 mul(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) mul() argument 719 mla(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) mla() argument 727 mls(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) mls() argument 735 smull(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) smull() argument 744 smull2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) smull2() argument 753 umull(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) umull() argument 762 umull2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) umull2() argument 771 smlal(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) smlal() argument 780 smlal2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) smlal2() argument 789 umlal(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) umlal() argument 798 umlal2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) umlal2() argument 807 smlsl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) smlsl() argument 816 smlsl2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) smlsl2() argument 825 umlsl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) umlsl() argument 834 umlsl2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) umlsl2() argument 843 sqdmull(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) sqdmull() argument 852 sqdmull2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) sqdmull2() argument 861 sqdmlal(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) sqdmlal() argument 870 sqdmlal2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) sqdmlal2() argument 879 sqdmlsl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) sqdmlsl() argument 888 sqdmlsl2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) sqdmlsl2() argument 897 sqdmulh(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) sqdmulh() argument 905 sqrdmulh(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) sqrdmulh() argument 924 pmul(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) pmul() argument 935 pmull(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) pmull() argument 948 pmull2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) pmull2() argument 962 sub(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) sub() argument 991 and_(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) and_() argument 1001 orr(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) orr() argument 1011 orn(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) orn() argument 1021 eor(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) eor() argument 1031 bic(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) bic() argument 1052 bif(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) bif() argument 1066 bit(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) bit() argument 1080 bsl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) bsl() argument 1094 SMinMax(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, bool max) SMinMax() argument 1112 smax(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) smax() argument 1118 smin(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) smin() argument 1124 SMinMaxP(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, bool max) SMinMaxP() argument 1149 smaxp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) smaxp() argument 1155 sminp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) sminp() argument 1244 UMinMax(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, bool max) UMinMax() argument 1262 umax(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) umax() argument 1268 umin(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) umin() argument 1274 UMinMaxP(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, bool max) UMinMaxP() argument 1299 umaxp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) umaxp() argument 1305 uminp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) uminp() argument 1544 sshl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) sshl() argument 1603 ushl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) ushl() argument 1829 AbsDiff(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, bool issigned) AbsDiff() argument 1847 saba(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) saba() argument 1857 uaba(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) uaba() argument 1976 ext(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) ext() argument 2321 uaddl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) uaddl() argument 2331 uaddl2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) uaddl2() argument 2341 uaddw(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) uaddw() argument 2350 uaddw2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) uaddw2() argument 2359 saddl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) saddl() argument 2369 saddl2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) saddl2() argument 2379 saddw(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) saddw() argument 2388 saddw2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) saddw2() argument 2397 usubl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) usubl() argument 2407 usubl2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) usubl2() argument 2417 usubw(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) usubw() argument 2426 usubw2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) usubw2() argument 2435 ssubl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) ssubl() argument 2445 ssubl2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) ssubl2() argument 2455 ssubw(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) ssubw() argument 2464 ssubw2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) ssubw2() argument 2473 uabal(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) uabal() argument 2483 uabal2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) uabal2() argument 2493 sabal(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) sabal() argument 2503 sabal2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) sabal2() argument 2513 uabdl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) uabdl() argument 2523 uabdl2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) uabdl2() argument 2533 sabdl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) sabdl() argument 2543 sabdl2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) sabdl2() argument 2553 umull(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) umull() argument 2563 umull2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) umull2() argument 2573 smull(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) smull() argument 2583 smull2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) smull2() argument 2593 umlsl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) umlsl() argument 2603 umlsl2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) umlsl2() argument 2613 smlsl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) smlsl() argument 2623 smlsl2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) smlsl2() argument 2633 umlal(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) umlal() argument 2643 umlal2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) umlal2() argument 2653 smlal(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) smlal() argument 2663 smlal2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) smlal2() argument 2673 sqdmlal(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) sqdmlal() argument 2681 sqdmlal2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) sqdmlal2() argument 2689 sqdmlsl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) sqdmlsl() argument 2697 sqdmlsl2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) sqdmlsl2() argument 2705 sqdmull(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) sqdmull() argument 2713 sqdmull2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) sqdmull2() argument 2721 sqrdmulh(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, bool round) sqrdmulh() argument 2748 sqdmulh(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) sqdmulh() argument 2754 addhn(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) addhn() argument 2758 add(VectorFormatDoubleWidth(vform), temp, src1, src2); addhn() local 2763 addhn2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) addhn2() argument 2772 raddhn(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) raddhn() argument 2776 add(VectorFormatDoubleWidth(vform), temp, src1, src2); raddhn() local 2781 raddhn2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) raddhn2() argument 2790 subhn(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) subhn() argument 2794 sub(VectorFormatDoubleWidth(vform), temp, src1, src2); subhn() local 2799 subhn2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) subhn2() argument 2808 rsubhn(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) rsubhn() argument 2812 sub(VectorFormatDoubleWidth(vform), temp, src1, src2); rsubhn() local 2817 rsubhn2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) rsubhn2() argument 2826 trn1(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) trn1() argument 2841 trn2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) trn2() argument 2856 zip1(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) zip1() argument 2871 zip2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) zip2() argument 2886 uzp1(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) uzp1() argument 2903 uzp2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) uzp2() argument 3277 fnmul(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) fnmul() argument 3286 frecps(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) frecps() argument 3299 frecps(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) frecps() argument 3312 frsqrts(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) frsqrts() argument 3384 frsqrts(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) frsqrts() argument 3397 fcmp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, Condition cond) fcmp() argument 3432 fcmp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, Condition cond) fcmp() argument 3460 fabscmp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, Condition cond) fabscmp() argument 3478 fmla(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) fmla() argument 3492 fmla(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) fmla() argument 3505 fmls(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) fmls() argument 3519 fmls(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) fmls() argument 3579 fabd(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) fabd() argument 3665 fmul(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) fmul() argument 3681 fmla(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) fmla() argument 3697 fmls(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) fmls() argument 3713 fmulx(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) fmulx() argument [all...] |
| /third_party/node/deps/v8/src/execution/s390/ |
| H A D | simulator-s390.cc | 3288 VectorBinaryOp(Simulator* sim, int dst, int src1, int src2, Operation op) VectorBinaryOp() argument 3434 VectorSum(Simulator* sim, int dst, int src1, int src2) VectorSum() argument 3528 VectorPack(Simulator* sim, int dst, int src1, int src2, bool saturate, const D& max = 0, const D& min = 0) VectorPack() argument 4189 int64_t src1 = get_simd_register_by_lane<int64_t>(r1, 0); EVALUATE() local 4400 FP_Type src1 = sim->get_fpr<FP_Type>(lhs); FPMinMaxForEachLane() local 4406 FP_Type src1 = sim->get_simd_register_by_lane<FP_Type>(lhs, i); FPMinMaxForEachLane() local 4446 VectorFPCompare(Simulator* sim, int dst, int src1, int src2, int m6, Operation op) VectorFPCompare() argument [all...] |
| /third_party/node/deps/v8/src/execution/riscv64/ |
| H A D | simulator-riscv64.cc | 3493 static inline bool is_invalid_fmul(T src1, T src2) { in is_invalid_fmul() argument 3499 static inline bool is_invalid_fadd(T src1, T src2) { in is_invalid_fadd() argument 3505 static inline bool is_invalid_fsub(T src1, T src2) { in is_invalid_fsub() argument 3511 static inline bool is_invalid_fdiv(T src1, argument 3516 is_invalid_fsqrt(T src1) is_invalid_fsqrt() argument [all...] |
| H A D | simulator-riscv64.h | 755 inline T CanonicalizeFPUOpFMA(Func fn, T dst, T src1, T src2) { in CanonicalizeFPUOpFMA() argument 772 T src1 = std::is_same<float, T>::value ? frs1() : drs1(); in CanonicalizeFPUOp3() local 790 T src1 = std::is_same<float, T>::value ? frs1() : drs1(); in CanonicalizeFPUOp2() local 806 T src1 = std::is_same<float, T>::value ? frs1() : drs1(); CanonicalizeFPUOp1() local [all...] |
| /third_party/node/deps/v8/src/wasm/baseline/ia32/ |
| H A D | liftoff-assembler-ia32.h | 1862 Register src1 = src.high_gp() == dst.low_gp() ? src.high_gp() : src.low_gp(); in emit_i64_popcnt() local [all...] |
| /third_party/node/deps/v8/src/wasm/baseline/arm/ |
| H A D | liftoff-assembler-arm.h | 1853 Register src1 = src.high_gp() == dst.low_gp() ? src.high_gp() : src.low_gp(); in emit_i64_popcnt() local 2475 emit_f64x2_replace_lane(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2, uint8_t imm_lane_idx) emit_f64x2_replace_lane() argument 2659 emit_f32x4_replace_lane(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2, uint8_t imm_lane_idx) emit_f32x4_replace_lane() argument 2845 emit_i64x2_replace_lane(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2, uint8_t imm_lane_idx) emit_i64x2_replace_lane() argument 2964 emit_i64x2_extmul_low_i32x4_s(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2) emit_i64x2_extmul_low_i32x4_s() argument 2971 emit_i64x2_extmul_low_i32x4_u(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2) emit_i64x2_extmul_low_i32x4_u() argument 2978 emit_i64x2_extmul_high_i32x4_s(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2) emit_i64x2_extmul_high_i32x4_s() argument 2985 emit_i64x2_extmul_high_i32x4_u(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2) emit_i64x2_extmul_high_i32x4_u() argument 3029 emit_i32x4_replace_lane(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2, uint8_t imm_lane_idx) emit_i32x4_replace_lane() argument [all...] |
| /third_party/node/deps/v8/src/wasm/baseline/arm64/ |
| H A D | liftoff-assembler-arm64.h | 1789 emit_f64x2_replace_lane(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2, uint8_t imm_lane_idx) emit_f64x2_replace_lane() argument 1930 emit_f32x4_replace_lane(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2, uint8_t imm_lane_idx) emit_f32x4_replace_lane() argument 2054 emit_i64x2_replace_lane(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2, uint8_t imm_lane_idx) emit_i64x2_replace_lane() argument 2145 emit_i64x2_extmul_low_i32x4_s(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2) emit_i64x2_extmul_low_i32x4_s() argument 2151 emit_i64x2_extmul_low_i32x4_u(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2) emit_i64x2_extmul_low_i32x4_u() argument 2157 emit_i64x2_extmul_high_i32x4_s(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2) emit_i64x2_extmul_high_i32x4_s() argument 2163 emit_i64x2_extmul_high_i32x4_u(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2) emit_i64x2_extmul_high_i32x4_u() argument 2205 emit_i32x4_replace_lane(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2, uint8_t imm_lane_idx) emit_i32x4_replace_lane() argument 2340 emit_i32x4_extmul_low_i16x8_s(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2) emit_i32x4_extmul_low_i16x8_s() argument 2346 emit_i32x4_extmul_low_i16x8_u(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2) emit_i32x4_extmul_low_i16x8_u() argument 2352 emit_i32x4_extmul_high_i16x8_s(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2) emit_i32x4_extmul_high_i16x8_s() argument 2358 emit_i32x4_extmul_high_i16x8_u(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2) emit_i32x4_extmul_high_i16x8_u() argument 2381 emit_i16x8_replace_lane(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2, uint8_t imm_lane_idx) emit_i16x8_replace_lane() argument 2524 VRegister src1 = lhs.fp(); emit_i8x16_shuffle() local 2582 emit_i8x16_replace_lane(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2, uint8_t imm_lane_idx) emit_i8x16_replace_lane() argument [all...] |