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/third_party/mesa3d/src/gallium/drivers/svga/
H A Dsvga_tgsi_insn.c361 emit_op2(struct svga_shader_emitter *emit, SVGA3dShaderInstToken inst, SVGA3dShaderDestToken dest, struct src_register src0, struct src_register src1) emit_op2() argument
376 emit_op3(struct svga_shader_emitter *emit, SVGA3dShaderInstToken inst, SVGA3dShaderDestToken dest, struct src_register src0, struct src_register src1, struct src_register src2) emit_op3() argument
393 emit_op4(struct svga_shader_emitter *emit, SVGA3dShaderInstToken inst, SVGA3dShaderDestToken dest, struct src_register src0, struct src_register src1, struct src_register src2, struct src_register src3) emit_op4() argument
521 submit_op2(struct svga_shader_emitter *emit, SVGA3dShaderInstToken inst, SVGA3dShaderDestToken dest, struct src_register src0, struct src_register src1) submit_op2() argument
570 submit_op3(struct svga_shader_emitter *emit, SVGA3dShaderInstToken inst, SVGA3dShaderDestToken dest, struct src_register src0, struct src_register src1, struct src_register src2) submit_op3() argument
642 submit_op4(struct svga_shader_emitter *emit, SVGA3dShaderInstToken inst, SVGA3dShaderDestToken dest, struct src_register src0, struct src_register src1, struct src_register src2, struct src_register src3) submit_op4() argument
1031 struct src_register src1 = get_fake_arl_const( emit ); emit_fake_arl() local
1172 const struct src_register src1 = emit_div() local
1216 const struct src_register src1 = emit_dp2() local
1436 emit_conditional(struct svga_shader_emitter *emit, enum pipe_compare_func compare_func, SVGA3dShaderDestToken dst, struct src_register src0, struct src_register src1, struct src_register pass, struct src_register fail) emit_conditional() argument
1565 struct src_register src1 = translate_src_register( emit_select_op() local
1583 const struct src_register src1 = emit_cmp() local
1807 struct src_register src1 = emit_tex() local
2060 const struct src_register src1 = translate_src_register(emit, &insn->Src[0]); emit_sqrt() local
2209 struct src_register src1 = translate_src_register( emit_pow() local
2245 submit_lrp(struct svga_shader_emitter *emit, SVGA3dShaderDestToken dst, struct src_register src0, struct src_register src1, struct src_register src2) submit_lrp() argument
2290 const struct src_register src1 = translate_src_register( emit_lrp() local
2320 const struct src_register src1 = translate_src_register( emit_dst_insn() local
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/third_party/mesa3d/src/mesa/main/
H A Dffvertex_prog.c570 emit_op3fn(struct tnl_program *p, enum prog_opcode op, struct ureg dest, GLuint mask, struct ureg src0, struct ureg src1, struct ureg src2, const char *fn, GLuint line) emit_op3fn() argument
/third_party/mesa3d/src/intel/vulkan/
H A Danv_blorp.c620 flip_coords(unsigned *src0, unsigned *src1, unsigned *dst0, unsigned *dst1) in flip_coords() argument
/third_party/mesa3d/src/nouveau/codegen/
H A Dnv50_ir_lowering_nvc0.cpp300 Value *src0[2], *src1[2]; in handleSET() local
H A Dnv50_ir_emit_gm107.cpp2780 int src1 = insn->predSrc == 1 ? 2 : 1; emitTEXs() local
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H A Dnv50_ir_emit_gk110.cpp1361 const int src1 = (i->predSrc == 1) ? 2 : 1; // if predSrc == 1, !srcExists(2) in emitTEX() local
1982 const int src1 = (i->predSrc == 1) ? 2 : 1; // if predSrc == 1, !srcExists(2) in emitPFETCH() local
H A Dnv50_ir_lowering_nv50.cpp65 ImmediateValue src1; in expandIntegerMUL() local
1182 Value *src1 in handleSLCT() local
1213 Value *src1 = bld.getSSA(); handleSELP() local
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/third_party/ltp/tools/sparse/sparse-src/
H A Dexample.c924 pseudo_t src1, src2; in generate_commutative_binop() local
1139 struct hardreg *src1, *src in generate_select() local
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H A Dsimplify.c629 static pseudo_t eval_op(int op, unsigned size, pseudo_t src1, pseudo_t src2) in eval_op() argument
818 pseudo_t src1 = or->src1; simplify_mask_or() local
1175 pseudo_t src1, src2; simplify_compare_constant() local
1593 pseudo_t src1 = insn->src1; simplify_const_leftsub() local
1831 pseudo_t src1 = *p1; simplify_add_one_side() local
1874 pseudo_t src1 = insn->src1; simplify_sub() local
1904 pseudo_t src1 = insn->src1; simplify_compare() local
1929 pseudo_t src1 = *p1; simplify_and_one_side() local
1994 pseudo_t src1 = *p1; simplify_ior_one_side() local
2048 pseudo_t src1 = *p1; simplify_xor_one_side() local
2428 pseudo_t cond, src1, src2; simplify_select() local
2575 pseudo_t src1, src2, src3; simplify_range() local
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/third_party/node/deps/v8/src/compiler/backend/arm64/
H A Dcode-generator-arm64.cc2252 src1 = i.InputSimd128Register(0).Format(f); in AssembleArchInstruction() local
2345 src1 = i.InputSimd128Register(0).Format(f); in AssembleArchInstruction() local
2367 VRegister src1 = i.InputSimd128Register(0); in AssembleArchInstruction() local
2515 src1 = i.InputSimd128Register(1); AssembleArchInstruction() local
2536 src1 = i.InputSimd128Register(1); AssembleArchInstruction() local
2577 src1 = i.InputSimd128Register(1); AssembleArchInstruction() local
2595 src1 = i.InputSimd128Register(1); AssembleArchInstruction() local
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/third_party/node/deps/v8/src/compiler/backend/mips64/
H A Dcode-generator-mips64.cc1364 FPURegister src1 = i.InputSingleRegister(0); in AssembleArchInstruction() local
1373 FPURegister src1 = i.InputDoubleRegister(0); in AssembleArchInstruction() local
1382 FPURegister src1 = i.InputSingleRegister(0); in AssembleArchInstruction() local
1391 FPURegister src1 = i.InputDoubleRegister(0); AssembleArchInstruction() local
2137 Simd128Register src1 = i.InputSimd128Register(1); AssembleArchInstruction() local
2160 Simd128Register src1 = i.InputSimd128Register(1); AssembleArchInstruction() local
2593 src1 = i.InputSimd128Register(1); AssembleArchInstruction() local
2646 Simd128Register src1 = i.InputSimd128Register(1); AssembleArchInstruction() local
2669 Simd128Register src1 = i.InputSimd128Register(1); AssembleArchInstruction() local
3360 src1 = i.InputSimd128Register(1); AssembleArchInstruction() local
3370 src1 = i.InputSimd128Register(1); AssembleArchInstruction() local
3380 src1 = i.InputSimd128Register(1); AssembleArchInstruction() local
3390 src1 = i.InputSimd128Register(1); AssembleArchInstruction() local
3400 src1 = i.InputSimd128Register(1); AssembleArchInstruction() local
3410 src1 = i.InputSimd128Register(1); AssembleArchInstruction() local
3420 src1 = i.InputSimd128Register(1); AssembleArchInstruction() local
3474 src1 = i.InputSimd128Register(1); AssembleArchInstruction() local
3484 src1 = i.InputSimd128Register(1); AssembleArchInstruction() local
3494 src1 = i.InputSimd128Register(1); AssembleArchInstruction() local
3504 src1 = i.InputSimd128Register(1); AssembleArchInstruction() local
3514 src1 = i.InputSimd128Register(1); AssembleArchInstruction() local
3524 src1 = i.InputSimd128Register(1); AssembleArchInstruction() local
3548 src1 = i.InputSimd128Register(1); AssembleArchInstruction() local
3558 src1 = i.InputSimd128Register(1); AssembleArchInstruction() local
3568 src1 = i.InputSimd128Register(1); AssembleArchInstruction() local
3578 src1 = i.InputSimd128Register(1); AssembleArchInstruction() local
3588 src1 = i.InputSimd128Register(1); AssembleArchInstruction() local
3598 src1 = i.InputSimd128Register(1); AssembleArchInstruction() local
3615 src1 = i.InputSimd128Register(1); AssembleArchInstruction() local
3725 Simd128Register src1 = i.InputSimd128Register(1); AssembleArchInstruction() local
3735 Simd128Register src1 = i.InputSimd128Register(1); AssembleArchInstruction() local
3762 Simd128Register src1 = i.InputSimd128Register(1); AssembleArchInstruction() local
3772 Simd128Register src1 = i.InputSimd128Register(1); AssembleArchInstruction() local
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/third_party/node/deps/v8/src/compiler/backend/ppc/
H A Dcode-generator-ppc.cc2397 Simd128Register src1 = i.InputSimd128Register(1); in AssembleArchInstruction() local
2451 Simd128Register src1 = i.InputSimd128Register(1); in AssembleArchInstruction() local
2811 Simd128Register src1 = i.InputSimd128Register(1); in AssembleArchInstruction() local
3088 src1 in AssembleArchInstruction() local
3140 src1 = i.InputSimd128Register(1), AssembleArchInstruction() local
3154 Simd128Register src1 = i.InputSimd128Register(1); AssembleArchInstruction() local
3164 Simd128Register src1 = i.InputSimd128Register(1); AssembleArchInstruction() local
3174 Simd128Register src1 = i.InputSimd128Register(1); AssembleArchInstruction() local
3184 Simd128Register src1 = i.InputSimd128Register(1); AssembleArchInstruction() local
3344 src1 = i.InputSimd128Register(1); AssembleArchInstruction() local
3352 src1 = i.InputSimd128Register(1); AssembleArchInstruction() local
3360 src1 = i.InputSimd128Register(1); AssembleArchInstruction() local
3368 src1 = i.InputSimd128Register(1); AssembleArchInstruction() local
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/third_party/node/deps/v8/src/compiler/backend/ia32/
H A Dcode-generator-ia32.cc2317 XMMRegister src1 = i.InputSimd128Register(0); in AssembleArchInstruction() local
2423 XMMRegister src1 = i.InputSimd128Register(0); in AssembleArchInstruction() local
2442 XMMRegister src1 = i.InputSimd128Register(0); in AssembleArchInstruction() local
2580 XMMRegister src1 = i.InputSimd128Register(0); AssembleArchInstruction() local
2638 XMMRegister src1 = i.InputSimd128Register(0); AssembleArchInstruction() local
2657 XMMRegister src1 = i.InputSimd128Register(0); AssembleArchInstruction() local
2873 XMMRegister src1 = i.InputSimd128Register(0); AssembleArchInstruction() local
2932 XMMRegister src1 = i.InputSimd128Register(0); AssembleArchInstruction() local
2950 XMMRegister src1 = i.InputSimd128Register(0); AssembleArchInstruction() local
3062 Operand src1 = i.InputOperand(1); AssembleArchInstruction() local
4417 Operand src1 = g.ToOperand(source); AssembleSwap() local
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/third_party/node/deps/v8/src/compiler/backend/mips/
H A Dcode-generator-mips.cc1350 FPURegister src1 = i.InputSingleRegister(0); in AssembleArchInstruction() local
1359 DoubleRegister src1 = i.InputDoubleRegister(0); in AssembleArchInstruction() local
1368 FPURegister src1 = i.InputSingleRegister(0); in AssembleArchInstruction() local
1377 DoubleRegister src1 = i.InputDoubleRegister(0); AssembleArchInstruction() local
3190 src1 = i.InputSimd128Register(1); AssembleArchInstruction() local
3200 src1 = i.InputSimd128Register(1); AssembleArchInstruction() local
3210 src1 = i.InputSimd128Register(1); AssembleArchInstruction() local
3220 src1 = i.InputSimd128Register(1); AssembleArchInstruction() local
3230 src1 = i.InputSimd128Register(1); AssembleArchInstruction() local
3240 src1 = i.InputSimd128Register(1); AssembleArchInstruction() local
3250 src1 = i.InputSimd128Register(1); AssembleArchInstruction() local
3304 src1 = i.InputSimd128Register(1); AssembleArchInstruction() local
3314 src1 = i.InputSimd128Register(1); AssembleArchInstruction() local
3324 src1 = i.InputSimd128Register(1); AssembleArchInstruction() local
3334 src1 = i.InputSimd128Register(1); AssembleArchInstruction() local
3344 src1 = i.InputSimd128Register(1); AssembleArchInstruction() local
3354 src1 = i.InputSimd128Register(1); AssembleArchInstruction() local
3378 src1 = i.InputSimd128Register(1); AssembleArchInstruction() local
3388 src1 = i.InputSimd128Register(1); AssembleArchInstruction() local
3398 src1 = i.InputSimd128Register(1); AssembleArchInstruction() local
3408 src1 = i.InputSimd128Register(1); AssembleArchInstruction() local
3418 src1 = i.InputSimd128Register(1); AssembleArchInstruction() local
3428 src1 = i.InputSimd128Register(1); AssembleArchInstruction() local
3445 src1 = i.InputSimd128Register(1); AssembleArchInstruction() local
3555 Simd128Register src1 = i.InputSimd128Register(1); AssembleArchInstruction() local
3565 Simd128Register src1 = i.InputSimd128Register(1); AssembleArchInstruction() local
3589 Simd128Register src1 = i.InputSimd128Register(1); AssembleArchInstruction() local
3599 Simd128Register src1 = i.InputSimd128Register(1); AssembleArchInstruction() local
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/third_party/node/deps/v8/src/compiler/backend/loong64/
H A Dcode-generator-loong64.cc1178 FPURegister src1 = i.InputSingleRegister(0); in AssembleArchInstruction() local
1187 FPURegister src1 = i.InputSingleRegister(0); in AssembleArchInstruction() local
1246 FPURegister src1 = i.InputDoubleRegister(0); in AssembleArchInstruction() local
1255 FPURegister src1 = i.InputDoubleRegister(0); AssembleArchInstruction() local
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/third_party/node/deps/v8/src/compiler/backend/riscv64/
H A Dcode-generator-riscv64.cc2755 src1 = i.InputSimd128Register(1); in AssembleArchInstruction() local
/third_party/node/deps/v8/src/codegen/arm64/
H A Dmacro-assembler-arm64-inl.h1137 void TurboAssembler::Push(const CPURegister& src0, const CPURegister& src1, in Push() argument
1159 void TurboAssembler::Push(const Register& src0, const VRegister& src1) { in Push() argument
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/third_party/mesa3d/src/intel/compiler/
H A Dbrw_eu_emit.c740 brw_alu2(struct brw_codegen *p, unsigned opcode, struct brw_reg dest, struct brw_reg src0, struct brw_reg src1) brw_alu2() argument
806 brw_alu3(struct brw_codegen *p, unsigned opcode, struct brw_reg dest, struct brw_reg src0, struct brw_reg src1, struct brw_reg src2) brw_alu3() argument
1150 brw_ADD(struct brw_codegen *p, struct brw_reg dest, struct brw_reg src0, struct brw_reg src1) brw_ADD() argument
1172 brw_AVG(struct brw_codegen *p, struct brw_reg dest, struct brw_reg src0, struct brw_reg src1) brw_AVG() argument
1193 brw_MUL(struct brw_codegen *p, struct brw_reg dest, struct brw_reg src0, struct brw_reg src1) brw_MUL() argument
1227 brw_LINE(struct brw_codegen *p, struct brw_reg dest, struct brw_reg src0, struct brw_reg src1) brw_LINE() argument
1237 brw_PLN(struct brw_codegen *p, struct brw_reg dest, struct brw_reg src0, struct brw_reg src1) brw_PLN() argument
1470 gfx6_IF(struct brw_codegen *p, enum brw_conditional_mod conditional, struct brw_reg src0, struct brw_reg src1) gfx6_IF() argument
1984 brw_CMP(struct brw_codegen *p, struct brw_reg dest, unsigned conditional, struct brw_reg src0, struct brw_reg src1) brw_CMP() argument
2013 brw_CMPN(struct brw_codegen *p, struct brw_reg dest, unsigned conditional, struct brw_reg src0, struct brw_reg src1) brw_CMPN() argument
2083 gfx6_math(struct brw_codegen *p, struct brw_reg dest, unsigned function, struct brw_reg src0, struct brw_reg src1) gfx6_math() argument
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/third_party/mesa3d/src/gallium/auxiliary/gallivm/
H A Dlp_bld_nir.c2186 LLVMValueRef src1 = NULL; in visit_intrinsic() local
/third_party/mesa3d/src/gallium/drivers/r600/sfn/
H A Dsfn_instr_alu.cpp96 AluInstr::AluInstr(EAluOp opcode, PRegister dest, PVirtualValue src0, PVirtualValue src1, in AluInstr() argument
104 AluInstr::AluInstr(ESDOp op, PVirtualValue src0, PVirtualValue src1, PVirtualValue address): in AluInstr() argument
1860 const nir_alu_src *src1 = &alu.src[1]; in emit_alu_op2() local
88 AluInstr(EAluOp opcode, PRegister dest, PVirtualValue src0, PVirtualValue src1, const std::set<AluModifiers>& m_flags) AluInstr() argument
2093 const nir_alu_src& src1 = alu.src[1]; emit_dot() local
2128 const nir_alu_src& src1 = alu.src[1]; emit_fdph() local
2429 const nir_alu_src& src1 = alu.src[1]; emit_alu_trans_op2_eg() local
2456 const nir_alu_src& src1 = alu.src[1]; emit_alu_trans_op2_cayman() local
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/third_party/pcre2/pcre2/src/sljit/
H A DsljitNativeARM_64.c1419 sljit_emit_op2(struct sljit_compiler *compiler, sljit_s32 op, sljit_s32 dst, sljit_sw dstw, sljit_s32 src1, sljit_sw src1w, sljit_s32 src2, sljit_sw src2w) sljit_emit_op2() argument
1471 sljit_emit_op2u(struct sljit_compiler *compiler, sljit_s32 op, sljit_s32 src1, sljit_sw src1w, sljit_s32 src2, sljit_sw src2w) sljit_emit_op2u() argument
1482 sljit_emit_shift_into(struct sljit_compiler *compiler, sljit_s32 op, sljit_s32 src_dst, sljit_s32 src1, sljit_sw src1w, sljit_s32 src2, sljit_sw src2w) sljit_emit_shift_into() argument
1721 sljit_emit_fop1_cmp(struct sljit_compiler *compiler, sljit_s32 op, sljit_s32 src1, sljit_sw src1w, sljit_s32 src2, sljit_sw src2w) sljit_emit_fop1_cmp() argument
1786 sljit_emit_fop2(struct sljit_compiler *compiler, sljit_s32 op, sljit_s32 dst, sljit_sw dstw, sljit_s32 src1, sljit_sw src1w, sljit_s32 src2, sljit_sw src2w) sljit_emit_fop2() argument
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/third_party/skia/third_party/externals/libwebp/src/dsp/
H A Denc_msa.c86 v16u8 srcl0, srcl1, src0 = { 0 }, src1 = { 0 }; in FTransform_MSA() local
717 v16u8 src0, src1, src2, src3, src4, src5, src6, src7; in SSE16x16_MSA() local
744 v16u8 src0, src1, src2, src3, src4, src5, src6, src7; in SSE16x8_MSA() local
763 v16u8 src0, src1, src2, src3, src4, src5, src6, src7; SSE8x8_MSA() local
783 uint32_t src0, src1, src2, src3, ref0, ref1, ref2, ref3; SSE4x4_MSA() local
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/third_party/skia/third_party/externals/libwebp/src/enc/
H A Dpicture_csp_enc.c291 static void UpdateChroma(const fixed_y_t* src1, const fixed_y_t* src2, in UpdateChroma() argument
489 fixed_y_t* const src1 = tmp_buffer + 0 * w; in PreprocessARGB() local
527 fixed_y_t* const src1 = tmp_buffer + 0 * w; PreprocessARGB() local
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/third_party/vixl/src/aarch64/
H A Dlogic-aarch64.cc507 cmp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, Condition cond) cmp() argument
551 cmp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, int imm, Condition cond) cmp() argument
562 cmptst(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) cmptst() argument
576 add(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) add() argument
606 add_uint(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, uint64_t value) add_uint() argument
635 addp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) addp() argument
649 sdiv(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) sdiv() argument
671 udiv(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) udiv() argument
691 mla(VectorFormat vform, LogicVRegister dst, const LogicVRegister& srca, const LogicVRegister& src1, const LogicVRegister& src2) mla() argument
703 mls(VectorFormat vform, LogicVRegister dst, const LogicVRegister& srca, const LogicVRegister& src1, const LogicVRegister& src2) mls() argument
715 mul(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) mul() argument
728 mul(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) mul() argument
739 smulh(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) smulh() argument
770 umulh(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) umulh() argument
801 mla(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) mla() argument
812 mls(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) mls() argument
822 sqdmull(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) sqdmull() argument
833 sqdmlal(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) sqdmlal() argument
844 sqdmlsl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) sqdmlsl() argument
855 sqdmulh(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) sqdmulh() argument
866 sqrdmulh(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) sqrdmulh() argument
877 sqrdmlah(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) sqrdmlah() argument
888 sqrdmlsh(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) sqrdmlsh() argument
915 pmul(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) pmul() argument
931 pmull(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) pmull() argument
950 pmull2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) pmull2() argument
968 sub(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) sub() argument
998 sub_uint(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, uint64_t value) sub_uint() argument
1027 and_(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) and_() argument
1039 orr(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) orr() argument
1051 orn(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) orn() argument
1063 eor(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) eor() argument
1075 bic(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) bic() argument
1104 bif(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) bif() argument
1120 bit(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) bit() argument
1136 bsl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src_mask, const LogicVRegister& src1, const LogicVRegister& src2) bsl() argument
1153 sminmax(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, bool max) sminmax() argument
1174 smax(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) smax() argument
1182 smin(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) smin() argument
1190 sminmaxp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, bool max) sminmaxp() argument
1221 smaxp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) smaxp() argument
1229 sminp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) sminp() argument
1359 uminmax(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, bool max) uminmax() argument
1380 umax(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) umax() argument
1388 umin(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) umin() argument
1396 uminmaxp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, bool max) uminmaxp() argument
1427 umaxp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) umaxp() argument
1435 uminp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) uminp() argument
1605 splice(VectorFormat vform, LogicVRegister dst, const LogicPRegister& pg, const LogicVRegister& src1, const LogicVRegister& src2) splice() argument
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/third_party/vixl/test/aarch32/
H A Dtest-assembler-aarch32.cc5462 const uint32_t src1[4] = {0x33333333, 0x44444444, 0x11111111, 0x22222222}; in TEST_A32() local

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