Searched defs:rev16 (Results 1 - 6 of 6) sorted by relevance
| /third_party/node/deps/v8/src/execution/arm64/ |
| H A D | simulator-logic-arm64.cc | 1912 LogicVRegister Simulator::rev16(VectorFormat vform, LogicVRegister dst, in rev16() function in v8::internal::Simulator
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| /third_party/vixl/src/aarch64/ |
| H A D | assembler-aarch64.cc | 1017 void Assembler::rev16(const Register& rd, const Register& rn) { in rev16() function in vixl::aarch64::Assembler
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| /third_party/node/deps/v8/src/codegen/arm64/ |
| H A D | assembler-arm64.cc | 1171 void Assembler::rev16(const Register& rd, const Register& rn) { in rev16() function in v8::internal::Assembler
1956 void Assembler::rev16(const VRegister& vd, const VRegister& vn) { in rev16() function in v8::internal::Assembler
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| /third_party/vixl/src/aarch32/ |
| H A D | assembler-aarch32.cc | 8897 void Assembler::rev16(Condition cond, in rev16() function in vixl::aarch32::Assembler
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| H A D | assembler-aarch32.h | 2875 void rev16(Register rd, Register rm) { rev16(al, Best, rd, rm); } in rev16() function in vixl::aarch32::Assembler
2876 void rev16(Condition cond, Register rd, Register rm) { in rev16() function in vixl::aarch32::Assembler
2879 void rev16(EncodingSize size, Register rd, Register rm) { in rev16() function in vixl::aarch32::Assembler
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| H A D | disasm-aarch32.cc | 2270 void Disassembler::rev16(Condition cond, in rev16() function in vixl::aarch32::Disassembler
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