| /third_party/mesa3d/src/intel/compiler/ |
| H A D | brw_ir_fs.h | 181 reg_offset(const fs_reg &r) in reg_offset() function
[all...] |
| H A D | brw_ir_vec4.h | 232 reg_offset(const backend_reg &r) in reg_offset() function
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| H A D | brw_vec4_visitor.cpp | 1119 int reg_offset = base_offset + orig_src.offset / REG_SIZE; in emit_scratch_read() local
1148 int reg_offset = base_offset + inst->dst.offset / REG_SIZE; in emit_scratch_write() local
1069 get_scratch_offset(bblock_t *block, vec4_instruction *inst, src_reg *reladdr, int reg_offset) get_scratch_offset() argument
[all...] |
| /third_party/mesa3d/src/amd/vulkan/winsys/amdgpu/ |
| H A D | radv_amdgpu_winsys.c | 125 radv_amdgpu_winsys_read_registers(struct radeon_winsys *rws, unsigned reg_offset, in radv_amdgpu_winsys_read_registers() argument
|
| /third_party/mesa3d/src/imagination/rogue/ |
| H A D | rogue_regalloc.c | 269 size_t reg_offset = reg_data->offset; in rogue_ra_alloc() local
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| /device/soc/rockchip/common/hardware/mpp/include/ |
| H A D | mpp_device.h | 86 MPP_RET (*reg_offset)(void *ctx, MppDevRegOffsetCfg *cfg); member
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| /device/soc/rockchip/rk3399/hardware/mpp/include/ |
| H A D | mpp_device.h | 86 MPP_RET (*reg_offset)(void *ctx, MppDevRegOffsetCfg *cfg); member
|
| /device/soc/rockchip/rk3568/hardware/mpp/include/ |
| H A D | mpp_device.h | 86 MPP_RET (*reg_offset)(void *ctx, MppDevRegOffsetCfg *cfg); member
|
| /third_party/ffmpeg/libavcodec/ |
| H A D | atrac3plusdsp.c | 127 waves_synth(Atrac3pWaveSynthParams *synth_param, Atrac3pWavesData *waves_info, Atrac3pWaveEnvelope *envelope, AVFloatDSPContext *fdsp, int invert_phase, int reg_offset, float *out) waves_synth() argument
|
| /third_party/mesa3d/src/gallium/winsys/radeon/drm/ |
| H A D | radeon_drm_winsys.c | 730 radeon_read_registers(struct radeon_winsys *rws, unsigned reg_offset, unsigned num_registers, uint32_t *out) radeon_read_registers() argument
|
| /third_party/mesa3d/src/gallium/winsys/amdgpu/drm/ |
| H A D | amdgpu_winsys.c | 289 amdgpu_read_registers(struct radeon_winsys *rws, unsigned reg_offset, unsigned num_registers, uint32_t *out) amdgpu_read_registers() argument
|
| /third_party/mesa3d/src/gallium/drivers/radeonsi/ |
| H A D | si_build_pm4.h | 308 static inline void radeon_set_sh_reg_func(struct radeon_cmdbuf *cs, unsigned reg_offset, in radeon_set_sh_reg_func() argument
316 static inline void radeon_set_sh_reg_idx3_func(struct radeon_cmdbuf *cs, unsigned reg_offset, in radeon_set_sh_reg_idx3_func() argument
|
| /third_party/mesa3d/src/gallium/drivers/r600/ |
| H A D | eg_debug.c | 133 ac_parse_set_reg_packet(FILE *f, uint32_t *ib, unsigned count, unsigned reg_offset) ac_parse_set_reg_packet() argument
|
| /device/soc/rockchip/common/vendor/drivers/gpu/arm/midgard/ |
| H A D | mali_kbase_device.c | 340 void kbase_device_trace_register_access(struct kbase_context *kctx, enum kbase_reg_access_type type, u16 reg_offset,
in kbase_device_trace_register_access() argument
|
| /device/soc/rockchip/rk3588/hardware/mpp/include/ |
| H A D | mpp_device.h | 117 MPP_RET (*reg_offset)(void *ctx, MppDevRegOffsetCfg *cfg); member
|
| /device/soc/rockchip/common/kernel/drivers/gpu/arm/midgard/ |
| H A D | mali_kbase_device.c | 331 void kbase_device_trace_register_access(struct kbase_context *kctx, enum kbase_reg_access_type type, u16 reg_offset, u32 reg_value) in kbase_device_trace_register_access() argument
|
| /third_party/elfutils/libdw/ |
| H A D | cfi.h | 127 reg_offset, /* DW_CFA_offset_extended et al */ enumerator
|
| /third_party/mesa3d/src/gallium/drivers/lima/ir/gp/ |
| H A D | regalloc.c | 397 unsigned reg_offset = ctx->alloc_start++; in find_free_value_reg() local
|
| /third_party/mesa3d/src/amd/common/ |
| H A D | ac_debug.c | 241 static void ac_parse_set_reg_packet(FILE *f, unsigned count, unsigned reg_offset, in ac_parse_set_reg_packet() argument
|
| H A D | ac_shader_util.c | 792 void ac_set_reg_cu_en(void *cs, unsigned reg_offset, uint32_t value, uint32_t clear_mask, in ac_set_reg_cu_en() argument
|
| H A D | ac_shadowed_regs.c | 4031 unsigned reg_offset = R_02835C_PA_SC_TILE_STEERING_OVERRIDE; in ac_emulate_clear_state() local
4050 ac_check_shadowed_regs(enum amd_gfx_level gfx_level, enum radeon_family family, unsigned reg_offset, unsigned count) ac_check_shadowed_regs() argument
[all...] |
| /device/soc/rockchip/common/kernel/drivers/gpu/arm/bifrost/jm/ |
| H A D | mali_kbase_jm_defs.h | 152 int reg_offset; member
|
| /device/soc/rockchip/common/vendor/drivers/gpu/arm/bifrost/jm/ |
| H A D | mali_kbase_jm_defs.h | 153 int reg_offset; member
|
| /device/soc/rockchip/rk3588/kernel/drivers/regulator/ |
| H A D | rk806-regulator.c | 360 int reg_offset = 0; in rk806_get_reg_offset() local
687 int reg_offset; in rk806_set_suspend_voltage_range() local
|
| /third_party/mesa3d/src/panfrost/midgard/ |
| H A D | midgard_ra.c | 45 offset_swizzle(unsigned *swizzle, unsigned reg_offset, unsigned srcshift, unsigned dstshift, unsigned dst_offset) in offset_swizzle() argument
|