| /third_party/node/deps/v8/src/regexp/x64/ |
| H A D | regexp-macro-assembler-x64.cc | 141 void RegExpMacroAssemblerX64::AdvanceRegister(int reg, int by) { in AdvanceRegister() argument
1113 void RegExpMacroAssemblerX64::IfRegisterGE(int reg, in IfRegisterGE() argument
1121 void RegExpMacroAssemblerX64::IfRegisterLT(int reg, in IfRegisterLT() argument
1129 void RegExpMacroAssemblerX64::IfRegisterEqPos(int reg, in IfRegisterEqPos() argument
1171 ReadCurrentPositionFromRegister(int reg) ReadCurrentPositionFromRegister() argument
1176 ReadPositionFromRegister(Register dst, int reg) ReadPositionFromRegister() argument
1182 WriteStackPointerToRegister(int reg) WriteStackPointerToRegister() argument
1190 ReadStackPointerFromRegister(int reg) ReadStackPointerFromRegister() argument
1224 WriteCurrentPositionToRegister(int reg, int cp_offset) WriteCurrentPositionToRegister() argument
[all...] |
| /third_party/mesa3d/src/gallium/drivers/freedreno/a6xx/ |
| H A D | fd6_program.c | 358 next_regid(uint32_t reg, uint32_t increment) in next_regid() argument
662 uint32_t reg = 0; variable
683 uint32_t reg variable
[all...] |
| /third_party/mesa3d/src/intel/compiler/ |
| H A D | brw_eu_validate.c | 1876 unsigned vstride, width, hstride, type_size, reg, subreg, address_mode; in special_requirements_for_handling_double_precision_data_types() local
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| /third_party/mesa3d/src/nouveau/codegen/ |
| H A D | nv50_ir_emit_nv50.cpp | 320 const Storage *reg = &dst->join->reg; in setDst() local
406 int reg = i->src(0).getIndirect(0)->rep()->reg.data.id; setSrcFileBits() local
466 const Storage *reg = &i->src(s).rep()->reg; setSrc() local
[all...] |
| /third_party/mesa3d/src/gallium/auxiliary/tgsi/ |
| H A D | tgsi_build.c | 1142 const struct tgsi_full_dst_register *reg = &full_inst->Dst[i]; in tgsi_build_full_instruction() local
1212 const struct tgsi_full_src_register *reg = &full_inst->Src[i]; tgsi_build_full_instruction() local
[all...] |
| /third_party/mesa3d/src/gallium/drivers/etnaviv/ |
| H A D | etnaviv_compiler_nir.c | 341 unsigned reg = ra_get_node_reg(c->g, c->live_map[src_index(c->impl, src)]); ra_src() local
[all...] |
| /third_party/mesa3d/src/gallium/drivers/nouveau/nvc0/ |
| H A D | nvc0_state.c | 217 uint32_t reg; in nvc0_rasterizer_state_create() local
|
| /third_party/mesa3d/src/gallium/drivers/r300/ |
| H A D | r300_emit.c | 521 unsigned reg, i, distx, disty, dist; in r300_get_mspos() local
|
| /third_party/mesa3d/src/gallium/drivers/r600/ |
| H A D | evergreen_compute.c | 380 unsigned reg = in r600_shader_binary_read_config() local
|
| /third_party/libbpf/src/ |
| H A D | usdt.c | 1332 unsigned int reg; in parse_usdt_arg() local
[all...] |
| /third_party/skia/third_party/externals/swiftshader/src/Renderer/ |
| H A D | VertexProcessor.hpp | 319 unsigned int reg; member
|
| /third_party/skia/third_party/externals/swiftshader/src/Shader/ |
| H A D | PixelProgram.cpp | 892 Vector4f reg; in fetchRegister() local
[all...] |
| H A D | VertexProgram.cpp | 690 Vector4f reg; in fetchRegister() local
[all...] |
| /third_party/skia/third_party/externals/swiftshader/third_party/subzero/src/ |
| H A D | IceAssemblerX8632.h | 130 explicit AsmOperand(GPRRegister reg) : fixup_(nullptr) { SetModRM(3, reg); } in AsmOperand() argument
952 emitRegisterOperand(int reg, int rm) emitRegisterOperand() argument
959 emitXmmRegisterOperand(RegType reg, RmType rm) emitXmmRegisterOperand() argument
[all...] |
| H A D | IceAssemblerX8664.h | 142 explicit AsmOperand(GPRRegister reg) : fixup_(nullptr) { SetModRM(3, reg); } in AsmOperand() argument
1029 emitRegisterOperand(int reg, int rm) emitRegisterOperand() argument
1036 emitXmmRegisterOperand(RegType reg, RmType rm) emitXmmRegisterOperand() argument
[all...] |
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/Disassembler/ |
| H A D | X86Disassembler.cpp | 601 uint8_t mod, rm, reg, evexrm; in readModRM() local
1756 translateRegister(MCInst &mcInst, Reg reg) translateRegister() argument
[all...] |
| H A D | X86DisassemblerDecoder.h | 621 Reg reg; member
|
| /third_party/toybox/toys/pending/ |
| H A D | vi.c | 644 static int vi_yank(char reg, size_t from, int flags) in vi_yank() argument
669 static int vi_delete(char reg, size_t from, int flags) in vi_delete() argument
695 static int vi_change(char reg, size_t to, int flags) in vi_change() argument
794 static int vi_yy(char reg, int count0, int count1) in vi_yy() argument
808 static int vi_dd(char reg, int count0, int count1) in vi_dd() argument
821 vi_x(char reg, int count0, int count1) vi_x() argument
1008 vi_push(char reg, int count0, int count1) vi_push() argument
1070 vi_o(char reg, int count0, int count1) vi_o() argument
1079 vi_O(char reg, int count0, int count1) vi_O() argument
1085 vi_D(char reg, int count0, int count1) vi_D() argument
1097 vi_I(char reg, int count0, int count1) vi_I() argument
1104 vi_join(char reg, int count0, int count1) vi_join() argument
1116 vi_find_next(char reg, int count0, int count1) vi_find_next() argument
[all...] |
| /third_party/vixl/src/aarch32/ |
| H A D | disasm-aarch32.h | 176 IndexedRegisterPrinter(DRegister reg, uint32_t index) in IndexedRegisterPrinter() argument
345 virtual DisassemblerStream& operator<<(Register reg) { in operator <<() argument
346 os_ << reg; in operator <<() local
349 virtual DisassemblerStream& operator<<(SRegister reg) { in operator <<() argument
350 os_ << reg; in operator <<() local
353 virtual DisassemblerStream& operator<<(DRegister reg) { in operator <<() argument
180 operator <<(std::ostream& os, IndexedRegisterPrinter reg) operator <<() argument
354 os_ << reg; operator <<() local
357 operator <<(QRegister reg) operator <<() argument
358 os_ << reg; operator <<() local
361 operator <<(const RegisterOrAPSR_nzcv reg) operator <<() argument
362 os_ << reg; operator <<() local
365 operator <<(SpecialRegister reg) operator <<() argument
366 os_ << reg; operator <<() local
369 operator <<(MaskedSpecialRegister reg) operator <<() argument
370 os_ << reg; operator <<() local
373 operator <<(SpecialFPRegister reg) operator <<() argument
374 os_ << reg; operator <<() local
377 operator <<(BankedRegister reg) operator <<() argument
378 os_ << reg; operator <<() local
397 operator <<(const DRegisterLane& reg) operator <<() argument
398 os_ << reg; operator <<() local
401 operator <<(const IndexedRegisterPrinter& reg) operator <<() argument
402 os_ << reg; operator <<() local
409 operator <<(CRegister reg) operator <<() argument
410 os_ << reg; operator <<() local
[all...] |
| /third_party/vixl/test/aarch64/ |
| H A D | test-utils-aarch64.cc | 177 bool Equal32(uint32_t expected, const RegisterDump* core, const Register& reg) { in Equal32() argument
193 Equal64(uint64_t reference, const RegisterDump* core, const Register& reg, ExpectedResult option) Equal64() argument
203 NotEqual64(uint64_t reference, const RegisterDump* core, const Register& reg) NotEqual64() argument
358 EqualSVELane(uint64_t expected, const RegisterDump* core, const ZRegister& reg, int lane) EqualSVELane() argument
387 EqualSVELane(uint64_t expected, const RegisterDump* core, const PRegister& reg, int lane) EqualSVELane() argument
720 CPURegister reg = scratch_registers.PopLowestIndex(); Dump() local
[all...] |
| /third_party/wpa_supplicant/wpa_supplicant-2.9/src/wps/ |
| H A D | wps_er.c | 1507 struct wps_registrar *reg = er->wps->registrar; in wps_er_set_sel_reg() local
|
| /third_party/wpa_supplicant/wpa_supplicant-2.9/wpa_supplicant/ |
| H A D | ap.c | 1018 struct wps_registrar *reg; in wpa_supplicant_ap_wps_cancel() local
|
| /third_party/wpa_supplicant/wpa_supplicant-2.9_standard/src/wps/ |
| H A D | wps_er.c | 1507 struct wps_registrar *reg = er->wps->registrar; in wps_er_set_sel_reg() local
|
| /third_party/wpa_supplicant/wpa_supplicant-2.9_standard/wpa_supplicant/ |
| H A D | ap.c | 1267 struct wps_registrar *reg; in wpa_supplicant_ap_wps_cancel() local
|
| /third_party/skia/third_party/externals/angle2/src/libANGLE/renderer/d3d/ |
| H A D | ProgramD3D.cpp | 259 unsigned int reg = variable
284 D3DUniform(GLenum type, HLSLRegisterType reg, const std::string &nameIn, const std::vector<unsigned int> &arraySizesIn, bool defaultBlock) D3DUniform() argument
|