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/third_party/mesa3d/src/gallium/drivers/svga/svgadump/
H A Dsvga_shader.h73 struct sh_reg reg; member
80 struct sh_reg reg; member
92 struct sh_reg reg; member
154 struct sh_dstreg reg; member
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/third_party/mesa3d/src/intel/compiler/
H A Dbrw_reg.h407 struct brw_reg reg; in brw_reg() local
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H A Dbrw_schedule_instructions.cpp904 int reg = inst->src[i].nr + off; in get_register_pressure_benefit() local
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/third_party/mesa3d/src/mesa/state_tracker/
H A Dst_atifs_to_nir.c334 unsigned reg = pass_tex - GL_REG_0_ATI; in compile_setupinst() local
/third_party/mesa3d/src/microsoft/compiler/
H A Ddxil_signature.h45 uint32_t reg; // Register Index (row index) member
/third_party/mesa3d/src/nouveau/codegen/
H A Dnv50_ir_build_util.cpp344 LValue *reg = new_LValue(func, f); mkClobber() local
350 LValue *reg = new_LValue(func, f); mkClobber() local
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/third_party/libdrm/tests/amdgpu/
H A Dvcn_tests.c75 static struct amdgpu_vcn_reg reg[] = { variable
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/third_party/node/deps/v8/src/codegen/arm/
H A Dmacro-assembler-arm.h509 void SmiUntag(Register reg, SBit s = LeaveCC) { in SmiUntag() argument
871 void DecodeField(Register reg) { in DecodeField() argument
H A Dassembler-arm-inl.h341 T reg = T::from_code(index); in CanAcquireVfp() local
355 T reg = T::from_code(index); in AcquireVfp() local
/third_party/node/deps/v8/src/codegen/x64/
H A Dassembler-x64-inl.h61 void Assembler::emit_rex_64(Register reg, Register rm_reg) { in emit_rex_64() argument
65 void Assembler::emit_rex_64(XMMRegister reg, Register rm_reg) { in emit_rex_64() argument
69 void Assembler::emit_rex_64(Register reg, XMMRegister rm_reg) { in emit_rex_64() argument
73 void Assembler::emit_rex_64(XMMRegister reg, XMMRegister rm_reg) { in emit_rex_64() argument
77 void Assembler::emit_rex_64(Register reg, Operand op) { in emit_rex_64() argument
81 emit_rex_64(XMMRegister reg, Operand op) emit_rex_64() argument
92 emit_rex_32(Register reg, Register rm_reg) emit_rex_32() argument
96 emit_rex_32(Register reg, Operand op) emit_rex_32() argument
104 emit_optional_rex_32(Register reg, Register rm_reg) emit_optional_rex_32() argument
109 emit_optional_rex_32(Register reg, Operand op) emit_optional_rex_32() argument
114 emit_optional_rex_32(XMMRegister reg, Operand op) emit_optional_rex_32() argument
119 emit_optional_rex_32(XMMRegister reg, XMMRegister base) emit_optional_rex_32() argument
124 emit_optional_rex_32(XMMRegister reg, Register base) emit_optional_rex_32() argument
129 emit_optional_rex_32(Register reg, XMMRegister base) emit_optional_rex_32() argument
146 emit_optional_rex_8(Register reg) emit_optional_rex_8() argument
153 emit_optional_rex_8(Register reg, Operand op) emit_optional_rex_8() argument
163 emit_vex3_byte1(XMMRegister reg, XMMRegister rm, LeadingOpcode m) emit_vex3_byte1() argument
170 emit_vex3_byte1(XMMRegister reg, Operand rm, LeadingOpcode m) emit_vex3_byte1() argument
176 emit_vex2_byte1(XMMRegister reg, XMMRegister v, VectorLength l, SIMDPrefix pp) emit_vex2_byte1() argument
188 emit_vex_prefix(XMMRegister reg, XMMRegister vreg, XMMRegister rm, VectorLength l, SIMDPrefix pp, LeadingOpcode mm, VexW w) emit_vex_prefix() argument
201 emit_vex_prefix(Register reg, Register vreg, Register rm, VectorLength l, SIMDPrefix pp, LeadingOpcode mm, VexW w) emit_vex_prefix() argument
210 emit_vex_prefix(XMMRegister reg, XMMRegister vreg, Operand rm, VectorLength l, SIMDPrefix pp, LeadingOpcode mm, VexW w) emit_vex_prefix() argument
223 emit_vex_prefix(Register reg, Register vreg, Operand rm, VectorLength l, SIMDPrefix pp, LeadingOpcode mm, VexW w) emit_vex_prefix() argument
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/third_party/node/deps/v8/src/maglev/
H A Dmaglev-regalloc.cc436 void StraightForwardRegisterAllocator::DropRegisterValue(Register reg) { in DropRegisterValue() argument
489 Register reg = registers.PopFirst(); InitializeConditionalBranchRegisters() local
549 Register reg = input.AssignedRegister(); TryAllocateToInput() local
604 Register reg = Register::from_code(operand.fixed_register_index()); AssignInput() local
644 Register reg = used_registers().first(); SpillAndClearRegisters() local
691 ForceAllocate( Register reg, ValueNode* node) ForceAllocate() argument
711 SetRegister(Register reg, ValueNode* node) SetRegister() argument
747 Register reg = used_registers().first(); InitializeRegisterValues() local
758 Register reg = entry.reg; InitializeRegisterValues() local
791 Register reg = entry.reg; InitializeBranchTargetRegisterValues() local
812 Register reg = entry.reg; MergeRegisterValues() local
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H A Dmaglev-interpreter-frame-state.h52 void set(interpreter::Register reg, ValueNode* value) { in set() argument
102 interpreter::Register reg = interpreter::Register::FromParameterIndex(i); ForEachParameter() local
110 interpreter::Register reg = interpreter::Register::FromParameterIndex(i); ForEachParameter() local
119 interpreter::Register reg = interpreter::Register(register_index); ForEachLocal() local
129 interpreter::Register reg = interpreter::Register(register_index); ForEachLocal() local
192 Register reg; global() member
229 CheckIsLoopPhiIfNeeded(const MaglevCompilationUnit& compilation_unit, int merge_offset, interpreter::Register reg, ValueNode* value) CheckIsLoopPhiIfNeeded() argument
468 NewLoopPhi(Zone* zone, interpreter::Register reg, int merge_offset) NewLoopPhi() argument
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/third_party/node/deps/v8/src/snapshot/embedded/
H A Dembedded-data.cc211 Register reg = descriptor.GetRegisterParameter(i); in BuiltinAliasesOffHeapTrampolineRegister() local
/third_party/mesa3d/src/gallium/drivers/freedreno/a5xx/
H A Dfd5_program.c229 next_regid(uint32_t reg, uint32_t increment) in next_regid() argument
456 uint32_t reg = 0; in fd5_program_emit() local
472 uint32_t reg in fd5_program_emit() local
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/third_party/mesa3d/src/gallium/drivers/i915/
H A Di915_fpc_translate.c72 negate(int reg, int x, int y, int z, int w) in negate() argument
/third_party/mesa3d/src/gallium/drivers/lima/ir/gp/
H A Dregalloc.c311 struct reg_info *reg = &ctx->registers[idx]; do_regalloc() local
401 unsigned reg = UINT_MAX; find_free_value_reg() local
447 unsigned reg = find_free_value_reg(ctx); handle_value_read() local
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/third_party/mesa3d/src/gallium/drivers/lima/ir/pp/
H A Ddisasm.c62 print_reg(ppir_codegen_vec4_reg reg, const char *special, FILE *fp) in print_reg() argument
89 print_vector_source(ppir_codegen_vec4_reg reg, const char *special, in print_vector_source() argument
105 print_source_scalar(unsigned reg, const char *special, bool abs, bool neg, FILE *fp) in print_source_scalar() argument
139 unsigned reg = (varying->imm.offset_vector << 2) + in print_varying_source() local
166 print_dest_scalar(unsigned reg, FILE *fp) print_dest_scalar() argument
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/third_party/mesa3d/src/gallium/auxiliary/gallivm/
H A Dlp_bld_tgsi_aos.c102 emit_fetch_constant( struct lp_build_tgsi_context * bld_base, const struct tgsi_full_src_register * reg, enum tgsi_opcode_type stype, unsigned swizzle) emit_fetch_constant() argument
173 emit_fetch_immediate( struct lp_build_tgsi_context * bld_base, const struct tgsi_full_src_register * reg, enum tgsi_opcode_type stype, unsigned swizzle) emit_fetch_immediate() argument
186 emit_fetch_input( struct lp_build_tgsi_context * bld_base, const struct tgsi_full_src_register * reg, enum tgsi_opcode_type stype, unsigned swizzle) emit_fetch_input() argument
200 emit_fetch_temporary( struct lp_build_tgsi_context * bld_base, const struct tgsi_full_src_register * reg, enum tgsi_opcode_type stype, unsigned swizzle) emit_fetch_temporary() argument
229 const struct tgsi_full_dst_register *reg = &inst->Dst[index]; lp_emit_store_aos() local
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H A Dlp_bld_nir_aos.c168 emit_load_reg(struct lp_build_nir_context *bld_base, struct lp_build_context *reg_bld, const nir_reg_src *reg, LLVMValueRef indir_src, LLVMValueRef reg_storage) emit_load_reg() argument
180 emit_store_reg(struct lp_build_nir_context *bld_base, struct lp_build_context *reg_bld, const nir_reg_dest *reg, unsigned writemask, LLVMValueRef indir_src, LLVMValueRef reg_storage, LLVMValueRef vals[NIR_MAX_VEC_COMPONENTS]) emit_store_reg() argument
/third_party/mesa3d/src/gallium/auxiliary/tgsi/
H A Dtgsi_transform.h248 tgsi_transform_dst_reg(struct tgsi_full_dst_register *reg, in tgsi_transform_dst_reg() argument
257 tgsi_transform_src_reg_xyzw(struct tgsi_full_src_register *reg, in tgsi_transform_src_reg_xyzw() argument
269 tgsi_transform_src_reg(struct tgsi_full_src_register *reg, in tgsi_transform_src_reg() argument
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/third_party/mesa3d/src/gallium/drivers/r600/sb/
H A Dsb_bc_parser.cpp941 region_node *reg = sh->create_region(); in prepare_loop() local
989 region_node *reg = sh->create_region(); in prepare_if() local
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/third_party/mesa3d/src/gallium/drivers/r300/compiler/
H A Dr3xx_vertprog.c806 static int swizzle_is_native(rc_opcode opcode, struct rc_src_register reg) in swizzle_is_native() argument
/third_party/pcre2/pcre2/src/sljit/
H A DsljitNativeX86_32.c1204 sljit_emit_mem(struct sljit_compiler *compiler, sljit_s32 type, sljit_s32 reg, sljit_s32 mem, sljit_sw memw) sljit_emit_mem() argument
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H A DsljitNativeX86_64.c33 static sljit_s32 emit_load_imm64(struct sljit_compiler *compiler, sljit_s32 reg, sljit_sw imm) in emit_load_imm64() argument
941 sljit_emit_mem(struct sljit_compiler *compiler, sljit_s32 type, sljit_s32 reg, sljit_s32 mem, sljit_sw memw) sljit_emit_mem() argument
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/MC/
H A DMCWin64EH.cpp334 uint8_t b, reg; in ARM64EmitUnwindCode() local
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