| /third_party/mesa3d/src/gallium/drivers/r600/sfn/ |
| H A D | sfn_debug.h | 60 reg = 1 << 6, enumerator
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| /third_party/mesa3d/src/intel/compiler/ |
| H A D | brw_clip.h | 89 } reg; member
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| H A D | brw_vec4_copy_propagation.cpp | 502 const unsigned reg = (alloc.offsets[inst->src[i].nr] + in opt_copy_propagation() local
514 const int reg = in opt_copy_propagation() local
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| H A D | gfx6_gs_visitor.cpp | 413 dst_reg reg = dst_reg(MRF, mrf); in emit_thread_end() local
501 int reg = 0; in setup_payload() local
[all...] |
| H A D | brw_vec4_tes.cpp | 51 int reg = 0; in setup_payload() local
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| /third_party/node/deps/base64/base64/test/ |
| H A D | benchmark.c | 41 char *reg; member
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| /third_party/mesa3d/src/panfrost/bifrost/test/ |
| H A D | test-constant-fold.cpp | 102 bi_index reg = bi_register(0); in TEST_F() local
123 bi_index reg = bi_register(0); in TEST_F() local
143 bi_index reg in TEST_F() local
157 bi_index reg = bi_register(0); TEST_F() local
174 bi_index reg = bi_register(0); TEST_F() local
193 bi_index reg = bi_register(0); TEST_F() local
204 bi_index reg = bi_register(0); TEST_F() local
[all...] |
| /third_party/mesa3d/src/panfrost/midgard/ |
| H A D | midgard_print.c | 49 int reg = SSA_REG_FROM_FIXED(source); in mir_print_index() local
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| /third_party/mesa3d/src/util/ |
| H A D | register_allocate_internal.h | 104 unsigned int reg; member
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| /third_party/mesa3d/src/panfrost/lib/ |
| H A D | pan_props.c | 254 unsigned reg = panfrost_query_raw(fd, in panfrost_query_afbc() local
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| /third_party/node/deps/v8/src/codegen/ |
| H A D | interface-descriptors.cc | 24 Register reg = registers[i]; in InitializeRegisters() local
120 bool CallInterfaceDescriptor::IsValidFloatParameterRegister(Register reg) { in IsValidFloatParameterRegister() argument
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| H A D | register-configuration.cc | 198 auto reg = Register::from_code(Default()->GetAllocatableGeneralCode(i)); in RestrictGeneralRegisters() local
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| /third_party/node/deps/v8/src/interpreter/ |
| H A D | bytecode-decoder.cc | 169 Register reg = in Decode() local
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| /third_party/mesa3d/src/gallium/drivers/iris/ |
| H A D | iris_perf.c | 59 iris_perf_store_register_mem(void *ctx, void *bo, uint32_t reg, uint32_t reg_size, uint32_t offset) iris_perf_store_register_mem() argument
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| /third_party/mesa3d/src/gallium/drivers/lima/ir/gp/ |
| H A D | reduce_scheduler.c | 71 float reg[n]; in schedule_calc_sched_info() local
[all...] |
| /third_party/mesa3d/src/gallium/drivers/lima/ir/pp/ |
| H A D | liveness.c | 81 ppir_reg *reg = ppir_src_get_reg(src); in ppir_liveness_instr_srcs() local
142 ppir_reg *reg = ppir_dest_get_reg(dest); in ppir_liveness_instr_dest() local
[all...] |
| /third_party/mesa3d/src/gallium/drivers/etnaviv/ |
| H A D | etnaviv_emit.h | 173 check_coalsence(struct etna_cmd_stream *stream, struct etna_coalesce *coalesce, uint32_t reg, uint32_t fixp) check_coalsence() argument
192 etna_coalsence_emit(struct etna_cmd_stream *stream, struct etna_coalesce *coalesce, uint32_t reg, uint32_t value) etna_coalsence_emit() argument
201 etna_coalsence_emit_fixp(struct etna_cmd_stream *stream, struct etna_coalesce *coalesce, uint32_t reg, uint32_t value) etna_coalsence_emit_fixp() argument
210 etna_coalsence_emit_reloc(struct etna_cmd_stream *stream, struct etna_coalesce *coalesce, uint32_t reg, const struct etna_reloc *r) etna_coalsence_emit_reloc() argument
[all...] |
| /third_party/mesa3d/src/panfrost/bifrost/ |
| H A D | bi_scoreboard.c | 121 unsigned reg = I->src[s].value; in bi_read_mask() local
144 unsigned reg = I->dest[d].value; in bi_write_mask() local
159 unsigned reg = I->src[0].value; in bi_write_mask() local
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| /third_party/mesa3d/src/gallium/auxiliary/tgsi/ |
| H A D | tgsi_dynamic_indexing.c | 105 remove_dynamic_indexes(struct tgsi_transform_context *ctx, struct tgsi_full_instruction *orig_inst, const struct tgsi_full_src_register *reg) remove_dynamic_indexes() argument
[all...] |
| H A D | tgsi_util.c | 54 tgsi_util_get_src_register_swizzle(const struct tgsi_src_register *reg, in tgsi_util_get_src_register_swizzle() argument
83 tgsi_util_set_src_register_swizzle(struct tgsi_src_register *reg, in tgsi_util_set_src_register_swizzle() argument
74 tgsi_util_get_full_src_register_swizzle( const struct tgsi_full_src_register *reg, unsigned component) tgsi_util_get_full_src_register_swizzle() argument
393 tgsi_util_get_src_from_ind(const struct tgsi_ind_register *reg) tgsi_util_get_src_from_ind() argument
[all...] |
| /third_party/mesa3d/src/gallium/drivers/d3d12/ |
| H A D | d3d12_root_signature.cpp | 62 init_constant_root_param(D3D12_ROOT_PARAMETER1 *param, unsigned reg, unsigned size, D3D12_SHADER_VISIBILITY visibility) init_constant_root_param() argument
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| /third_party/mesa3d/src/gallium/drivers/freedreno/a2xx/ |
| H A D | fd2_draw.c | 227 uint32_t reg; variable
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| /third_party/mesa3d/src/gallium/drivers/r300/compiler/ |
| H A D | r300_fragprog_swizzle.c | 109 static int r300_swizzle_is_native(rc_opcode opcode, struct rc_src_register reg) in r300_swizzle_is_native() argument
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| H A D | radeon_program_tex.c | 38 struct rc_src_register reg = { 0, 0, 0, 0, 0, 0 }; in shadow_fail_value() local
49 struct rc_src_register reg = { 0, 0, 0, 0, 0, 0 }; in shadow_pass_value() local
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| /third_party/mesa3d/src/gallium/drivers/r300/ |
| H A D | r300_vs_draw.c | 78 static void emit_temp(struct tgsi_transform_context *ctx, unsigned reg) in emit_temp() argument
88 emit_output(struct tgsi_transform_context *ctx, unsigned name, unsigned index, unsigned interp, unsigned reg) emit_output() argument
|