| /third_party/mesa3d/src/imagination/rogue/ |
| H A D | rogue_operand.h | 128 } reg; member
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| /third_party/mesa3d/src/intel/compiler/ |
| H A D | brw_ir_vec4.h | 57 retype(src_reg reg, enum brw_reg_type type) in retype() argument
66 add_byte_offset(backend_reg *reg, unsigned bytes) in add_byte_offset() argument
100 byte_offset(src_reg reg, unsigned bytes) byte_offset() argument
107 offset(src_reg reg, unsigned width, unsigned delta) offset() argument
115 horiz_offset(src_reg reg, unsigned delta) horiz_offset() argument
125 swizzle(src_reg reg, unsigned swizzle) swizzle() argument
136 negate(src_reg reg) negate() argument
144 is_uniform(const src_reg ®) is_uniform() argument
174 retype(dst_reg reg, enum brw_reg_type type) retype() argument
181 byte_offset(dst_reg reg, unsigned bytes) byte_offset() argument
188 offset(dst_reg reg, unsigned width, unsigned delta) offset() argument
196 horiz_offset(const dst_reg ®, unsigned delta) horiz_offset() argument
205 writemask(dst_reg reg, unsigned mask) writemask() argument
[all...] |
| H A D | brw_compile_ff_gs.c | 64 } reg; member
[all...] |
| H A D | brw_vec4_gs_visitor.cpp | 60 struct brw_reg reg; in attribute_to_hw_reg() local
110 struct brw_reg reg = in setup_varying_inputs() local
136 int reg = 0; setup_payload() local
[all...] |
| H A D | brw_vec4_tcs.cpp | 54 int reg = 0; in setup_payload() local
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| H A D | brw_vec4_reg_allocate.cpp | 33 assign(unsigned int *reg_hw_locations, backend_reg *reg) in assign() argument
208 int reg = choose_spill_reg(g); in reg_allocate() local
[all...] |
| /third_party/mesa3d/src/gallium/drivers/vc4/ |
| H A D | vc4_qpu_disasm.c | 248 get_special_write_desc(int reg, bool is_a) in get_special_write_desc() argument
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| /third_party/mesa3d/src/imagination/vulkan/ |
| H A D | pvr_hw_pass.h | 94 } reg; member
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| /third_party/mesa3d/src/gallium/drivers/r600/sfn/ |
| H A D | sfn_optimizer.cpp | 624 auto reg = new Register(vreg.sel(), override_chan, vreg[index]->pin()); in visit() local
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| /third_party/mesa3d/src/gallium/drivers/radeonsi/ |
| H A D | radeon_vcn_dec.h | 89 } reg; member
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| /third_party/mesa3d/src/gallium/drivers/svga/svgadump/ |
| H A D | svga_shader_dump.c | 150 static void dump_reg( struct sh_reg reg, struct sh_srcreg *indreg, const struct dump_info *di ) in dump_reg() argument
133 format_reg(const char *name, const struct sh_reg reg, const struct sh_srcreg *indreg) format_reg() argument
367 struct sh_reg reg; dump_dstreg() member
[all...] |
| /third_party/mesa3d/src/nouveau/codegen/ |
| H A D | nv50_ir_target.cpp | 428 CodeEmitter::addInterp(int ipa, int reg, FixupApply apply) in addInterp() argument
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| /third_party/mesa3d/src/panfrost/bifrost/valhall/ |
| H A D | va_insert_flow.c | 77 unsigned reg = I->src[s].value; in bi_read_mask() local
97 unsigned reg = I->dest[d].value; in bi_write_mask() local
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| /third_party/node/deps/v8/src/baseline/ |
| H A D | baseline-assembler-inl.h | 102 void BaselineAssembler::SmiUntag(Register reg) { __ SmiUntag(reg); } in SmiUntag() argument
157 Register reg = scratch.AcquireScratch(); in ~EnsureAccumulatorPreservedScope() local
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| /third_party/node/deps/v8/src/codegen/loong64/ |
| H A D | constants-loong64.h | 87 int reg; member
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| /third_party/node/deps/v8/src/codegen/ |
| H A D | reglist-base.h | 48 constexpr void set(RegisterT reg) { in set() argument
53 constexpr void clear(RegisterT reg) { in clear() argument
126 RegisterT reg = first(); PopFirst() local
222 RegisterT reg = reglist.first(); operator <<() local
[all...] |
| /third_party/node/deps/v8/src/codegen/riscv64/ |
| H A D | constants-riscv64.h | 107 int reg; member
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| /third_party/node/deps/v8/src/execution/ |
| H A D | simulator-base.h | 175 static void* ReverseRedirection(intptr_t reg) { in ReverseRedirection() argument
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| /third_party/node/deps/v8/src/deoptimizer/ |
| H A D | translation-array.cc | 213 void TranslationArrayBuilder::StoreRegister(Register reg) { in StoreRegister() argument
219 void TranslationArrayBuilder::StoreInt32Register(Register reg) { in StoreInt32Register() argument
226 void TranslationArrayBuilder::StoreInt64Register(Register reg) { in StoreInt64Register() argument
233 void TranslationArrayBuilder::StoreUint32Register(Register reg) { in StoreUint32Register() argument
239 void TranslationArrayBuilder::StoreBoolRegister(Register reg) { in StoreBoolRegister() argument
246 StoreFloatRegister(FloatRegister reg) StoreFloatRegister() argument
252 StoreDoubleRegister(DoubleRegister reg) StoreDoubleRegister() argument
[all...] |
| /third_party/node/deps/v8/src/interpreter/ |
| H A D | bytecode-register-optimizer.h | 139 RegisterInfo* GetRegisterInfo(Register reg) { in GetRegisterInfo() argument
144 RegisterInfo* GetOrCreateRegisterInfo(Register reg) { in GetOrCreateRegisterInfo() argument
149 NewRegisterInfo(Register reg) NewRegisterInfo() argument
[all...] |
| /third_party/node/deps/v8/src/torque/ls/ |
| H A D | message-handler.cc | 234 Registration reg = request.params().add_registrations(); in HandleInitializedNotification() local
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| /third_party/mesa3d/src/gallium/drivers/freedreno/a4xx/ |
| H A D | fd4_program.c | 319 uint32_t reg = 0; in fd4_program_emit() local
335 uint32_t reg = 0; in fd4_program_emit() local
[all...] |
| /third_party/mesa3d/src/gallium/drivers/freedreno/a6xx/ |
| H A D | fd6_context.h | 129 unsigned reg = REG_A6XX_CP_SCRATCH_REG(scratch_idx); in emit_marker6() local
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| /third_party/mesa3d/src/gallium/drivers/i915/ |
| H A D | i915_fpc_emit.c | 47 i915_release_temp(struct i915_fp_compile *p, int reg) in i915_release_temp() argument
79 uint32_t reg = UREG(type, nr); in i915_emit_decl() local
261 unsigned reg, idx; i915_emit_const1f() local
291 unsigned reg, idx; i915_emit_const2f() local
330 unsigned reg; i915_emit_const4f() local
[all...] |
| /third_party/mesa3d/src/gallium/drivers/lima/ir/gp/ |
| H A D | nir.c | 35 gpir_reg *reg = ralloc(comp, gpir_reg); in gpir_create_reg() local
44 gpir_reg *reg = comp->reg_for_reg[index]; in reg_for_nir_reg() local
118 gpir_reg *reg = NULL; gpir_node_find() local
[all...] |