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Searched defs:operand (Results 226 - 250 of 274) sorted by relevance

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/third_party/node/deps/v8/src/compiler/backend/s390/
H A Dcode-generator-s390.cc2284 MemOperand operand = i.MemoryOperand(&mode); AssembleArchInstruction() local
2316 MemOperand operand = i.MemoryOperand(&mode); AssembleArchInstruction() local
2346 MemOperand operand = i.MemoryOperand(&mode, &index); AssembleArchInstruction() local
2370 MemOperand operand = i.MemoryOperand(&mode, &index); AssembleArchInstruction() local
3177 MemOperand operand = i.MemoryOperand(&mode, &index); AssembleArchInstruction() local
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H A Dinstruction-selector-s390.cc213 GetEffectiveAddressMemoryOperand( Node* operand, InstructionOperand inputs[], size_t* input_count, OperandModes immediate_mode = OperandMode::kInt20Imm) GetEffectiveAddressMemoryOperand() argument
/third_party/node/deps/v8/src/codegen/ia32/
H A Dmacro-assembler-ia32.cc1686 Operand operand = in CallRecordWriteStub() local
1701 Operand operand = in CallRecordWriteStub() local
/third_party/node/deps/v8/src/interpreter/
H A Dbytecode-array-builder.cc192 uint32_t operand = static_cast<uint32_t>(reg.ToOperand()); in OutputLdarRaw() local
198 uint32_t operand = static_cast<uint32_t>(reg.ToOperand()); in OutputStarRaw() local
/third_party/node/deps/v8/src/maglev/
H A Dmaglev-ir.h295 const compiler::InstructionOperand& operand() const { return operand_; } in operand() function in v8::internal::maglev::ValueLocation
296 const compiler::InstructionOperand& operand() { return operand_; } in operand() function in v8::internal::maglev::ValueLocation
713 void Spill(compiler::AllocatedOperand operand) { in Spill() argument
/third_party/skia/third_party/externals/swiftshader/src/OpenGL/compiler/
H A DOutputASM.cpp2830 sw::Shader::ParameterType OutputASM::registerType(TIntermTyped *operand) in registerType() argument
2902 hasFlatQualifier(TIntermTyped *operand) hasFlatQualifier() argument
2908 registerIndex(TIntermTyped *operand) registerIndex() argument
3499 isSamplerRegister(TIntermTyped *operand) isSamplerRegister() argument
3504 arrayExceedsLimits(TIntermTyped *operand) arrayExceedsLimits() argument
3899 TIntermSymbol *operand = binaryTerminal->getLeft()->getAsSymbolNode(); LoopInfo() local
3924 TIntermSymbol *operand = unaryTerminal->getOperand()->getAsSymbolNode(); LoopInfo() local
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H A DParseHelper.cpp254 void TParseContext::unaryOpError(const TSourceLoc &line, const char* op, TString operand) in unaryOpError() argument
257 extraInfoStream << "no operation '" << op << "' exists that takes an operand of type " << operand in unaryOpError() local
3608 TIntermNode *operand in addFunctionCallOrMethod() local
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H A Dintermediate.h530 TIntermTyped* operand; member in TIntermUnary
/third_party/python/Include/internal/
H A Dpycore_ast.h368 expr_ty operand; member
/third_party/vixl/src/aarch64/
H A Dmacro-assembler-aarch64.cc816 void MacroAssembler::Tst(const Register& rn, const Operand& operand) { in Emit() argument
818 Ands(AppropriateZeroRegFor(rn), rn, operand); in Emit() local
800 And(const Register& rd, const Register& rn, const Operand& operand) Emit() argument
808 Ands(const Register& rd, const Register& rn, const Operand& operand) Emit() argument
822 Bic(const Register& rd, const Register& rn, const Operand& operand) Emit() argument
830 Bics(const Register& rd, const Register& rn, const Operand& operand) Emit() argument
838 Orr(const Register& rd, const Register& rn, const Operand& operand) Emit() argument
846 Orn(const Register& rd, const Register& rn, const Operand& operand) Emit() argument
854 Eor(const Register& rd, const Register& rn, const Operand& operand) Emit() argument
862 Eon(const Register& rd, const Register& rn, const Operand& operand) Emit() argument
870 LogicalMacro(const Register& rd, const Register& rn, const Operand& operand, LogicalOp op) Emit() argument
993 Mov(const Register& rd, const Operand& operand, DiscardMoveMode discard_mode) Emit() argument
1208 Mvn(const Register& rd, const Operand& operand) Emit() argument
1238 Ccmp(const Register& rn, const Operand& operand, StatusFlags nzcv, Condition cond) Emit() argument
1251 Ccmn(const Register& rn, const Operand& operand, StatusFlags nzcv, Condition cond) Emit() argument
1264 ConditionalCompareMacro(const Register& rn, const Operand& operand, StatusFlags nzcv, Condition cond, ConditionalCompareOp op) Emit() argument
1487 Add(const Register& rd, const Register& rn, const Operand& operand, FlagsUpdate S) Emit() argument
1504 Adds(const Register& rd, const Register& rn, const Operand& operand) Emit() argument
1575 Sub(const Register& rd, const Register& rn, const Operand& operand, FlagsUpdate S) Emit() argument
1592 Subs(const Register& rd, const Register& rn, const Operand& operand) Emit() argument
1599 Cmn(const Register& rn, const Operand& operand) Emit() argument
1601 Adds(AppropriateZeroRegFor(rn), rn, operand); Emit() local
1605 Cmp(const Register& rn, const Operand& operand) Emit() argument
1607 Subs(AppropriateZeroRegFor(rn), rn, operand); Emit() local
1750 Neg(const Register& rd, const Operand& operand) Emit() argument
1760 Negs(const Register& rd, const Operand& operand) Emit() argument
1887 AddSubMacro(const Register& rd, const Register& rn, const Operand& operand, FlagsUpdate S, AddSubOp op) Emit() argument
1941 Adc(const Register& rd, const Register& rn, const Operand& operand) Emit() argument
1949 Adcs(const Register& rd, const Register& rn, const Operand& operand) Emit() argument
1957 Sbc(const Register& rd, const Register& rn, const Operand& operand) Emit() argument
1965 Sbcs(const Register& rd, const Register& rn, const Operand& operand) Emit() argument
1973 Ngc(const Register& rd, const Operand& operand) Emit() argument
1980 Ngcs(const Register& rd, const Operand& operand) Emit() argument
1987 AddSubWithCarryMacro(const Register& rd, const Register& rn, const Operand& operand, FlagsUpdate S, AddSubWithCarryOp op) Emit() argument
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/third_party/glslang/SPIRV/
H A DSpvBuilder.cpp2608 void Builder::createNoResultOp(Op opCode, Id operand) in createNoResultOp() argument
2656 Id Builder::createUnaryOp(Op opCode, Id typeId, Id operand) in createUnaryOp() argument
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/third_party/mesa3d/src/amd/compiler/
H A Daco_optimizer.cpp659 alu_can_accept_constant(aco_opcode opcode, unsigned operand) in alu_can_accept_constant() argument
682 valu_can_accept_vgpr(aco_ptr<Instruction>& instr, unsigned operand) in valu_can_accept_vgpr() argument
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/third_party/mesa3d/src/compiler/glsl/
H A Dast_to_hir.cpp1208 get_scalar_boolean_operand(exec_list *instructions, struct _mesa_glsl_parse_state *state, ast_expression *parent_expr, int operand, const char *operand_name, bool *error_emitted) get_scalar_boolean_operand() argument
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/third_party/node/deps/v8/src/compiler/backend/x64/
H A Dinstruction-selector-x64.cc198 GetEffectiveAddressMemoryOperand( Node* operand, InstructionOperand inputs[], size_t* input_count, RegisterUseKind reg_kind = RegisterUseKind::kUseRegister) GetEffectiveAddressMemoryOperand() argument
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/third_party/node/deps/v8/src/compiler/backend/
H A Dinstruction.h743 set_source(const InstructionOperand& operand) set_source() argument
747 set_destination(const InstructionOperand& operand) set_destination() argument
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H A Dmid-tier-register-allocator.cc395 AllocatedOperand operand; member
543 void VirtualRegisterData::DefineAsConstantOperand(ConstantOperand* operand, in DefineAsConstantOperand() argument
551 DefineAsFixedSpillOperand( AllocatedOperand* operand, int virtual_register, MachineRepresentation rep, int instr_index, bool is_deferred_block, bool is_exceptional_call_output) DefineAsFixedSpillOperand() argument
642 SpillOperand(InstructionOperand* operand, int instr_index, bool has_constant_policy, MidTierRegisterAllocationData* data) SpillOperand() argument
968 PendingUse(InstructionOperand* operand, int virtual_register, bool can_be_constant, int instr_index) PendingUse() argument
1166 Commit(RegisterIndex reg, AllocatedOperand allocated, InstructionOperand* operand, MidTierRegisterAllocationData* data) Commit() argument
1200 AllocateUse(RegisterIndex reg, int virtual_register, InstructionOperand* operand, int instr_index, MidTierRegisterAllocationData* data) AllocateUse() argument
1207 AllocatePendingUse(RegisterIndex reg, int virtual_register, InstructionOperand* operand, bool can_be_constant, int instr_index) AllocatePendingUse() argument
2238 CommitRegister(RegisterIndex reg, int virtual_register, MachineRepresentation rep, InstructionOperand* operand, UsePosition pos) CommitRegister() argument
2336 AllocateUse( RegisterIndex reg, VirtualRegisterData& virtual_register, InstructionOperand* operand, int instr_index, UsePosition pos) AllocateUse() argument
2350 AllocatePendingUse( RegisterIndex reg, VirtualRegisterData& virtual_register, InstructionOperand* operand, bool can_be_constant, int instr_index) AllocatePendingUse() argument
2365 AllocateUseWithMove( RegisterIndex reg, VirtualRegisterData& virtual_register, UnallocatedOperand* operand, int instr_index, UsePosition pos) AllocateUseWithMove() argument
2378 AllocateInput( UnallocatedOperand* operand, VirtualRegisterData& virtual_register, int instr_index) AllocateInput() argument
2455 AllocateGapMoveInput( UnallocatedOperand* operand, VirtualRegisterData& vreg_data, int instr_index) AllocateGapMoveInput() argument
2470 AllocateConstantOutput( ConstantOperand* operand, VirtualRegisterData& vreg_data, int instr_index) AllocateConstantOutput() argument
2482 AllocateOutput(UnallocatedOperand* operand, VirtualRegisterData& vreg_data, int instr_index) AllocateOutput() argument
2488 AllocateOutput( UnallocatedOperand* operand, VirtualRegisterData& vreg_data, int instr_index, UsePosition pos) AllocateOutput() argument
2583 AllocateTemp(UnallocatedOperand* operand, int virtual_register, MachineRepresentation rep, int instr_index) AllocateTemp() argument
2622 ReserveFixedInputRegister( const UnallocatedOperand* operand, int virtual_register, MachineRepresentation rep, int instr_index) ReserveFixedInputRegister() argument
2630 ReserveFixedTempRegister( const UnallocatedOperand* operand, int virtual_register, MachineRepresentation rep, int instr_index) ReserveFixedTempRegister() argument
2637 ReserveFixedOutputRegister( const UnallocatedOperand* operand, int virtual_register, MachineRepresentation rep, int instr_index) ReserveFixedOutputRegister() argument
2644 ReserveFixedRegister( const UnallocatedOperand* operand, int virtual_register, MachineRepresentation rep, int instr_index, UsePosition pos) ReserveFixedRegister() argument
2710 InstructionOperand operand; AllocatePhiGapMove() local
3162 IsFixedRegisterPolicy( const UnallocatedOperand* operand) IsFixedRegisterPolicy() argument
3172 const UnallocatedOperand* operand = ReserveFixedRegisters() local
3191 const UnallocatedOperand* operand = ReserveFixedRegisters() local
3205 const UnallocatedOperand* operand = ReserveFixedRegisters() local
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/third_party/node/deps/v8/src/compiler/backend/ia32/
H A Dinstruction-selector-ia32.cc2480 InstructionOperand operand = g.UseRegister(node->InputAt(0)); in VisitI64x2ReplaceLaneI32Pair() local
/third_party/node/deps/v8/src/codegen/arm64/
H A Dmacro-assembler-arm64.cc155 LogicalMacro(const Register& rd, const Register& rn, const Operand& operand, LogicalOp op) LogicalMacro() argument
339 Mov(const Register& rd, const Operand& operand, DiscardMoveMode discard_mode) Mov() argument
579 Mvn(const Register& rd, const Operand& operand) Mvn() argument
631 ConditionalCompareMacro(const Register& rn, const Operand& operand, StatusFlags nzcv, Condition cond, ConditionalCompareOp op) ConditionalCompareMacro() argument
659 Csel(const Register& rd, const Register& rn, const Operand& operand, Condition cond) Csel() argument
765 AddSubMacro(const Register& rd, const Register& rn, const Operand& operand, FlagsUpdate S, AddSubOp op) AddSubMacro() argument
811 AddSubWithCarryMacro(const Register& rd, const Register& rn, const Operand& operand, FlagsUpdate S, AddSubWithCarryOp op) AddSubWithCarryMacro() argument
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/third_party/node/deps/v8/src/codegen/x64/
H A Dassembler-x64.cc169 Operand::Operand(Operand operand, int32_t offset) { in Operand() argument
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/third_party/node/deps/v8/src/execution/arm64/
H A Dsimulator-logic-arm64.cc4108 uint64_t operand; in ursqrte() local
4138 uint64_t operand; in urecpe() local
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/third_party/node/deps/v8/src/execution/riscv64/
H A Dsimulator-riscv64.h196 inline int32_t operand() const { return operand_; } in operand() function in v8::internal::SimInstructionBase
/third_party/node/deps/v8/src/wasm/baseline/ia32/
H A Dliftoff-assembler-ia32.h2700 EmitSimdShiftOp(LiftoffAssembler* assm, LiftoffRegister dst, LiftoffRegister operand, LiftoffRegister count) EmitSimdShiftOp() argument
2720 EmitSimdShiftOpImm(LiftoffAssembler* assm, LiftoffRegister dst, LiftoffRegister operand, int32_t count) EmitSimdShiftOpImm() argument
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/third_party/skia/third_party/externals/angle2/src/common/spirv/
H A Dspirv_instruction_builder_autogen.cpp840 WriteCopyObject(Blob *blob, IdResultType idResultType, IdResult idResult, IdRef operand) WriteCopyObject() argument
1320 WriteBitcast(Blob *blob, IdResultType idResultType, IdResult idResult, IdRef operand) WriteBitcast() argument
1329 WriteSNegate(Blob *blob, IdResultType idResultType, IdResult idResult, IdRef operand) WriteSNegate() argument
1338 WriteFNegate(Blob *blob, IdResultType idResultType, IdResult idResult, IdRef operand) WriteFNegate() argument
1789 WriteLogicalNot(Blob *blob, IdResultType idResultType, IdResult idResult, IdRef operand) WriteLogicalNot() argument
2206 WriteNot(Blob *blob, IdResultType idResultType, IdResult idResult, IdRef operand) WriteNot() argument
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/third_party/skia/third_party/externals/angle2/src/compiler/translator/
H A DOutputSPIRV.cpp3100 TIntermTyped *operand = node->getChildNode(0)->getAsTyped(); in createCompare() local
/third_party/skia/third_party/externals/tint/src/writer/spirv/
H A Dbuilder.cc2753 Operand operand; in GenerateTextureIntrinsic() member

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