| /third_party/mesa3d/src/panfrost/midgard/ |
| H A D | midgard_schedule.c | 66 add_dependency(struct util_dynarray *table, unsigned index, uint16_t mask, midgard_instruction **instructions, unsigned child) in add_dependency() argument
88 mark_access(struct util_dynarray *table, unsigned index, uint16_t mask, unsigned parent) in mark_access() argument
127 unsigned mask = mir_bytemask(instructions[i]); in mir_create_dependency_graph() local
213 is_single_component_mask(unsigned mask) in is_single_component_mask() argument
376 unsigned mask; global() member
667 unsigned mask = predicate->mask; mir_choose_instruction() local
[all...] |
| H A D | midgard_ra.c | 402 unsigned mask = mir_bytemask(ins); in mir_compute_interference() local
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| /third_party/mesa3d/src/nouveau/codegen/ |
| H A D | nv50_ir_driver.h | 42 unsigned mask : 4; /* vec4 mask */ member
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| /third_party/mesa3d/src/util/ |
| H A D | xmlconfig.c | 262 uint32_t size = 1 << cache->tableSize, mask = size - 1; in findOption() local
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| /third_party/mesa3d/src/gallium/drivers/llvmpipe/ |
| H A D | lp_bld_depth.c | 242 lp_build_stencil_op(struct lp_build_context *bld, const struct pipe_stencil_state stencil[2], enum stencil_op op, LLVMValueRef stencilRefs[2], LLVMValueRef stencilVals, LLVMValueRef mask, LLVMValueRef front_facing) lp_build_stencil_op() argument
353 get_z_shift_and_mask(const struct util_format_description *format_desc, unsigned *shift, unsigned *width, unsigned *mask) get_z_shift_and_mask() argument
391 get_s_shift_and_mask(const struct util_format_description *format_desc, unsigned *shift, unsigned *mask) get_s_shift_and_mask() argument
825 lp_build_depth_stencil_test(struct gallivm_state *gallivm, const struct lp_depth_state *depth, const struct pipe_stencil_state stencil[2], struct lp_type z_src_type, const struct util_format_description *format_desc, struct lp_build_mask_context *mask, LLVMValueRef *cov_mask, LLVMValueRef stencil_refs[2], LLVMValueRef z_src, LLVMValueRef z_fb, LLVMValueRef s_fb, LLVMValueRef face, LLVMValueRef *z_value, LLVMValueRef *s_value, boolean do_branch, bool restrict_depth) lp_build_depth_stencil_test() argument
970 LLVMValueRef mask = lp_build_const_int_vec(gallivm, s_type, s_mask); lp_build_depth_stencil_test() local
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| H A D | lp_linear_sampler.c | 599 const __m128i mask = _mm_set1_epi32(0xff000000); in fetch_bgrx_axis_aligned_linear() local
618 const __m128i mask = _mm_set1_epi32(0xff000000); in fetch_bgrx_clamp_linear() local
638 const __m128i mask = _mm_set1_epi32(0xff000000); in fetch_bgrx_linear() local
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| H A D | lp_rast.h | 256 uint64_t mask; member
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| /third_party/mesa3d/src/gallium/drivers/nouveau/nv50/ |
| H A D | nv50_state.c | 69 nv50_colormask(unsigned mask) in nv50_colormask() argument
1251 unsigned mask = 0; in nv50_bind_images_range() local
1344 unsigned mask = 0; nv50_bind_buffers_range() local
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| /third_party/icu/icu4c/source/tools/icuexportdata/ |
| H A D | icuexportdata.cpp | 256 uint16_t mask = 0; in dumpScriptExtensions() local
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| /third_party/libevdev/libevdev/ |
| H A D | libevdev.c | 1325 const unsigned long *mask = NULL; in libevdev_has_event_code() local
1574 unsigned long *mask = NULL; in libevdev_enable_event_code() local
1621 unsigned long *mask = NULL; in libevdev_disable_event_code() local
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| /third_party/ltp/tools/sparse/sparse-src/ |
| H A D | expand.c | 84 long long mask = 1ULL << (expr->ctype->bit_size - 1); in get_longlong() local
102 long long value, mask, signmask; in cast_value() local
194 unsigned long long v, l, r, mask; in simplify_int_binop() local
310 unsigned long long l, r, mask; simplify_cmp_binop() local
767 unsigned long long v, mask; simplify_preop() local
1376 long long value, mask; __get_expression_value() local
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| /third_party/lwip/src/netif/ppp/ |
| H A D | ipcp.c | 531 u32_t mask; local
1887 u32_t mask; in ipcp_up() local
[all...] |
| /third_party/node/deps/v8/src/compiler/ |
| H A D | common-operator.h | 281 BitMaskType mask() const { return bit_mask_; } in mask() function in v8::internal::compiler::final
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| H A D | machine-operator-reducer.cc | 1209 uint32_t const mask = divisor - 1; in ReduceInt32Mod() local
1615 uint32_t mask = mleft.right().ResolvedValue(); in ReduceWord32Shr() local
1706 typename A::intN_t const mask = m.right().ResolvedValue(); in ReduceWordNAnd() member in v8::internal::compiler::A
1789 uint32_t const mask; global() member
1815 uint32_t mask = mand.right().ResolvedValue(); Detect() local
1867 uint32_t mask = 1 << shift.right().ResolvedValue(); TryDetectShiftAndMaskOneBit() local
2361 auto mask = mand.right().ResolvedValue(); ReduceWord32EqualForConstantRhs() local
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| /third_party/node/deps/v8/src/compiler/backend/arm/ |
| H A D | code-generator-arm.cc | 2467 Simd128Register mask = i.TempSimd128Register(0); in AssembleArchInstruction() local
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| /third_party/node/deps/v8/src/baseline/ia32/ |
| H A D | baseline-assembler-ia32-inl.h | 146 void BaselineAssembler::TestAndBranch(Register value, int mask, Condition cc, in TestAndBranch() argument
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| /third_party/node/deps/v8/src/baseline/mips/ |
| H A D | baseline-assembler-mips-inl.h | 140 void BaselineAssembler::TestAndBranch(Register value, int mask, Condition cc, in TestAndBranch() argument
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| /third_party/node/deps/v8/src/baseline/loong64/ |
| H A D | baseline-assembler-loong64-inl.h | 138 void BaselineAssembler::TestAndBranch(Register value, int mask, Condition cc, in TestAndBranch() argument
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| /third_party/node/deps/v8/src/codegen/ |
| H A D | code-stub-assembler.cc | 562 constexpr uintptr_t mask[] = {static_cast<uintptr_t>(0x5555555555555555), in PopulationCountFallback() local
[all...] |
| /third_party/node/deps/v8/src/codegen/s390/ |
| H A D | macro-assembler-s390.h | 968 uint64_t mask = (static_cast<uint64_t>(1) << width) - 1; in ExtractBitRange() local
973 uint32_t mask = (1 << width) - 1; in ExtractBitRange() local
985 inline void ExtractBitMask(Register dst, Register src, uintptr_t mask, in ExtractBitMask() argument
1022 TestBitMask(Register value, uintptr_t mask, Register scratch = r0) TestBitMask() argument
[all...] |
| /third_party/node/deps/v8/src/baseline/s390/ |
| H A D | baseline-assembler-s390-inl.h | 236 void BaselineAssembler::TestAndBranch(Register value, int mask, Condition cc, in TestAndBranch() argument
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| /third_party/node/deps/v8/src/baseline/riscv64/ |
| H A D | baseline-assembler-riscv64-inl.h | 136 void BaselineAssembler::TestAndBranch(Register value, int mask, Condition cc, in TestAndBranch() argument
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| /third_party/node/deps/v8/src/baseline/mips64/ |
| H A D | baseline-assembler-mips64-inl.h | 138 void BaselineAssembler::TestAndBranch(Register value, int mask, Condition cc, in TestAndBranch() argument
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| /third_party/node/deps/v8/src/baseline/ppc/ |
| H A D | baseline-assembler-ppc-inl.h | 236 void BaselineAssembler::TestAndBranch(Register value, int mask, Condition cc, in TestAndBranch() argument
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| /third_party/node/deps/v8/src/baseline/arm/ |
| H A D | baseline-assembler-arm-inl.h | 151 void BaselineAssembler::TestAndBranch(Register value, int mask, Condition cc, in TestAndBranch() argument
|