| /arkcompiler/runtime_core/static_core/runtime/interpreter/ |
| H A D | frame.h | 202 ALWAYS_INLINE inline void SetNextInstruction(BytecodeInstruction inst) in SetNextInstruction() argument
212 ALWAYS_INLINE inline void SetInstruction(const uint8_t *inst) in SetInstruction() argument
492 ALWAYS_INLINE inline void SetNextInstruction(BytecodeInstruction inst) in SetNextInstruction() argument
502 ALWAYS_INLINE inline void SetInstruction(const uint8_t *inst) in SetInstruction() argument
|
| /arkcompiler/runtime_core/static_core/runtime/tooling/ |
| H A D | debugger.cpp | 666 static Field *ResolveField(ManagedThread *thread, const Method *caller, const BytecodeInstruction &inst) in ResolveField() argument
[all...] |
| /third_party/glslang/SPIRV/ |
| H A D | spvIR.h | 205 void addLocalVariable(std::unique_ptr<Instruction> inst) { localVariables.push_back(std::move(inst)); } in addLocalVariable() argument
509 __inline void Function::addLocalVariable(std::unique_ptr<Instruction> inst) in addLocalVariable() argument
523 __inline void Block::addInstruction(std::unique_ptr<Instruction> inst) in addInstruction() argument
[all...] |
| /third_party/mesa3d/src/compiler/glsl/ |
| H A D | glsl_to_nir.cpp | 1272 ir_instruction *inst = (ir_instruction *) param; in visit() local
1572 ir_instruction *inst = (ir_instruction *) param; in visit() local
[all...] |
| H A D | ir_reader.cpp | 360 ir_instruction *inst = NULL; in read_instruction() local
[all...] |
| /third_party/mesa3d/src/compiler/nir/ |
| H A D | nir_loop_analyze.c | 355 nir_intrinsic_instr *inst = nir_instr_as_intrinsic(instr); in is_only_uniform_src() local
461 nir_instr *inst = biv->def_outside_loop->parent_instr; in compute_induction_information() local
|
| /third_party/mesa3d/src/broadcom/compiler/ |
| H A D | vir_register_allocate.c | 136 can_reconstruct_inst(struct qinst *inst) in can_reconstruct_inst() argument
91 qinst_writes_tmu(const struct v3d_device_info *devinfo, struct qinst *inst) qinst_writes_tmu() argument
100 is_end_of_tmu_sequence(const struct v3d_device_info *devinfo, struct qinst *inst, struct qblock *block) is_end_of_tmu_sequence() argument
444 struct qinst *inst = vir_ADD_dest(c, tmua, c->spill_base, offset); v3d_emit_spill_tmua() local
490 v3d_emit_tmu_spill(struct v3d_compile *c, struct qinst *inst, struct qreg spill_temp, struct qinst *position, uint32_t ip, uint32_t spill_offset) v3d_emit_tmu_spill() argument
945 update_graph_and_reg_classes_for_inst(struct v3d_compile *c, int *acc_nodes, struct qinst *inst) update_graph_and_reg_classes_for_inst() argument
[all...] |
| /third_party/mesa3d/src/amd/vulkan/ |
| H A D | radv_debug.c | 271 struct radv_shader_inst *inst = &instructions[*num]; in si_add_split_disasm() local
340 struct radv_shader_inst *inst = &instructions[i]; radv_dump_annotated_shader() local
946 struct radv_shader_inst *inst = &instructions[i]; radv_dump_faulty_shader() local
[all...] |
| /third_party/mesa3d/src/intel/compiler/ |
| H A D | brw_fs_generator.cpp | 58 brw_reg_from_fs_reg(const struct intel_device_info *devinfo, fs_inst *inst, in brw_reg_from_fs_reg() argument
321 fs_generator::generate_send(fs_inst *inst, in generate_send() argument
357 fire_fb_write(fs_inst *inst, struct brw_reg payload, struct brw_reg implied_header, GLuint nr) fire_fb_write() argument
399 generate_fb_write(fs_inst *inst, struct brw_reg payload) generate_fb_write() argument
442 generate_fb_read(fs_inst *inst, struct brw_reg dst, struct brw_reg payload) generate_fb_read() argument
456 generate_mov_indirect(fs_inst *inst, struct brw_reg dst, struct brw_reg reg, struct brw_reg indirect_byte_offset) generate_mov_indirect() argument
599 generate_shuffle(fs_inst *inst, struct brw_reg dst, struct brw_reg src, struct brw_reg idx) generate_shuffle() argument
718 generate_quad_swizzle(const fs_inst *inst, struct brw_reg dst, struct brw_reg src, unsigned swiz) generate_quad_swizzle() argument
788 generate_cs_terminate(fs_inst *inst, struct brw_reg payload) generate_cs_terminate() argument
840 generate_linterp(fs_inst *inst, struct brw_reg dst, struct brw_reg *src) generate_linterp() argument
946 generate_get_buffer_size(fs_inst *inst, struct brw_reg dst, struct brw_reg src, struct brw_reg surf_index) generate_get_buffer_size() argument
991 generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg surface_index, struct brw_reg sampler_index) generate_tex() argument
1245 generate_ddx(const fs_inst *inst, struct brw_reg dst, struct brw_reg src) generate_ddx() argument
1301 generate_ddy(const fs_inst *inst, struct brw_reg dst, struct brw_reg src) generate_ddy() argument
1384 generate_scratch_write(fs_inst *inst, struct brw_reg src) generate_scratch_write() argument
1424 generate_scratch_read(fs_inst *inst, struct brw_reg dst) generate_scratch_read() argument
1434 generate_scratch_read_gfx7(fs_inst *inst, struct brw_reg dst) generate_scratch_read_gfx7() argument
1480 generate_scratch_header(fs_inst *inst, struct brw_reg dst) generate_scratch_header() argument
1512 generate_uniform_pull_constant_load(fs_inst *inst, struct brw_reg dst, struct brw_reg index, struct brw_reg offset) generate_uniform_pull_constant_load() argument
1533 generate_uniform_pull_constant_load_gfx7(fs_inst *inst, struct brw_reg dst, struct brw_reg index, struct brw_reg payload) generate_uniform_pull_constant_load_gfx7() argument
1594 generate_varying_pull_constant_load_gfx4(fs_inst *inst, struct brw_reg dst, struct brw_reg index) generate_varying_pull_constant_load_gfx4() argument
1652 generate_pixel_interpolator_query(fs_inst *inst, struct brw_reg dst, struct brw_reg src, struct brw_reg msg_data, unsigned msg_type) generate_pixel_interpolator_query() argument
1680 generate_set_sample_id(fs_inst *inst, struct brw_reg dst, struct brw_reg src0, struct brw_reg src1) generate_set_sample_id() argument
[all...] |
| H A D | brw_lower_logical_sends.cpp | 34 lower_urb_read_logical_send(const fs_builder &bld, fs_inst *inst) in lower_urb_read_logical_send() argument
79 lower_urb_write_logical_send(const fs_builder &bld, fs_inst *inst) lower_urb_write_logical_send() argument
151 lower_fb_write_logical_send(const fs_builder &bld, fs_inst *inst, const struct brw_wm_prog_data *prog_data, const brw_wm_prog_key *key, const fs_visitor::thread_payload &payload) lower_fb_write_logical_send() argument
413 lower_fb_read_logical_send(const fs_builder &bld, fs_inst *inst) lower_fb_read_logical_send() argument
467 lower_sampler_logical_send_gfx4(const fs_builder &bld, fs_inst *inst, opcode op, const fs_reg &coordinate, const fs_reg &shadow_c, const fs_reg &lod, const fs_reg &lod2, const fs_reg &surface, const fs_reg &sampler, unsigned coord_components, unsigned grad_components) lower_sampler_logical_send_gfx4() argument
574 lower_sampler_logical_send_gfx5(const fs_builder &bld, fs_inst *inst, opcode op, const fs_reg &coordinate, const fs_reg &shadow_c, const fs_reg &lod, const fs_reg &lod2, const fs_reg &sample_index, const fs_reg &surface, const fs_reg &sampler, unsigned coord_components, unsigned grad_components) lower_sampler_logical_send_gfx5() argument
776 fs_inst *inst = bld.LOAD_PAYLOAD(dst, src_comps, length, header_size); emit_load_payload_with_padding() local
783 lower_sampler_logical_send_gfx7(const fs_builder &bld, fs_inst *inst, opcode op, const fs_reg &coordinate, const fs_reg &shadow_c, fs_reg lod, const fs_reg &lod2, const fs_reg &min_lod, const fs_reg &sample_index, const fs_reg &mcs, const fs_reg &surface, const fs_reg &sampler, const fs_reg &surface_handle, const fs_reg &sampler_handle, const fs_reg &tg4_offset, unsigned payload_type_bit_size, unsigned coord_components, unsigned grad_components) lower_sampler_logical_send_gfx7() argument
1243 lower_sampler_logical_send(const fs_builder &bld, fs_inst *inst, opcode op) lower_sampler_logical_send() argument
1295 emit_predicate_on_vector_mask(const fs_builder &bld, fs_inst *inst) emit_predicate_on_vector_mask() argument
1326 setup_surface_descriptors(const fs_builder &bld, fs_inst *inst, uint32_t desc, const fs_reg &surface, const fs_reg &surface_handle) setup_surface_descriptors() argument
1359 lower_surface_logical_send(const fs_builder &bld, fs_inst *inst) lower_surface_logical_send() argument
1672 lower_lsc_surface_logical_send(const fs_builder &bld, fs_inst *inst) lower_lsc_surface_logical_send() argument
1833 lower_surface_block_logical_send(const fs_builder &bld, fs_inst *inst) lower_surface_block_logical_send() argument
1929 emit_fragment_mask(const fs_builder &bld, fs_inst *inst) emit_fragment_mask() argument
1949 lower_lsc_a64_logical_send(const fs_builder &bld, fs_inst *inst) lower_lsc_a64_logical_send() argument
2059 lower_a64_logical_send(const fs_builder &bld, fs_inst *inst) lower_a64_logical_send() argument
2215 lower_lsc_varying_pull_constant_logical_send(const fs_builder &bld, fs_inst *inst) lower_lsc_varying_pull_constant_logical_send() argument
2294 lower_varying_pull_constant_logical_send(const fs_builder &bld, fs_inst *inst) lower_varying_pull_constant_logical_send() argument
2386 lower_math_logical_send(const fs_builder &bld, fs_inst *inst) lower_math_logical_send() argument
2416 lower_btd_logical_send(const fs_builder &bld, fs_inst *inst) lower_btd_logical_send() argument
2486 lower_trace_ray_logical_send(const fs_builder &bld, fs_inst *inst) lower_trace_ray_logical_send() argument
[all...] |
| H A D | brw_fs_visitor.cpp | 52 fs_inst *inst = bld.emit(SHADER_OPCODE_TXF_MCS_LOGICAL, dest, srcs, in emit_mcs_fetch() local
669 fs_inst *inst = NULL; in emit_fb_writes() local
945 fs_inst *inst = abld.emit(SHADER_OPCODE_URB_WRITE_LOGICAL, reg_undef, emit_urb_writes() local
990 fs_inst *inst = bld.emit(SHADER_OPCODE_URB_WRITE_LOGICAL, reg_undef, emit_urb_writes() local
1041 fs_inst *inst = bld.exec_all().emit(SHADER_OPCODE_URB_WRITE_LOGICAL, emit_urb_writes() local
1081 fs_inst *inst = bld.exec_all() emit_cs_terminate() local
[all...] |
| H A D | brw_mesh.cpp | 914 fs_inst *inst = bld8.emit(SHADER_OPCODE_URB_WRITE_LOGICAL, in emit_urb_direct_writes() local
942 fs_inst *inst = bld8.emit(SHADER_OPCODE_URB_WRITE_LOGICAL, in emit_urb_direct_writes() local
1008 fs_inst *inst = bld8.emit(SHADER_OPCODE_URB_WRITE_LOGICAL, in emit_urb_indirect_writes() local
1046 fs_inst *inst = ubld8.emit(SHADER_OPCODE_URB_READ_LOGICAL, data, emit_urb_direct_reads() local
1108 fs_inst *inst = bld8.emit(SHADER_OPCODE_URB_READ_LOGICAL, emit_urb_indirect_reads() local
[all...] |
| H A D | brw_vec4.cpp | 723 is_dep_ctrl_unsafe(const vec4_instruction *inst) is_dep_ctrl_unsafe() argument
1314 const vec4_instruction *inst = (const vec4_instruction *)be_inst; dump_instruction() local
1673 is_align1_df(vec4_instruction *inst) is_align1_df() argument
1866 get_lowered_simd_width(const struct intel_device_info *devinfo, enum shader_dispatch_mode dispatch_mode, unsigned stage, const vec4_instruction *inst) get_lowered_simd_width() argument
1928 dst_src_regions_overlap(vec4_instruction *inst) dst_src_regions_overlap() argument
2077 is_gfx7_supported_64bit_swizzle(vec4_instruction *inst, unsigned arg) is_gfx7_supported_64bit_swizzle() argument
2107 is_supported_64bit_region(vec4_instruction *inst, unsigned arg) is_supported_64bit_region() argument
2266 apply_logical_swizzle(struct brw_reg *hw_reg, vec4_instruction *inst, int arg) apply_logical_swizzle() argument
[all...] |
| H A D | brw_vec4_nir.cpp | 102 vec4_instruction *inst = emit(MOV(dst_null_d(), condition)); in nir_emit_if() local
435 vec4_instruction *inst = new(mem_ctx) in nir_emit_intrinsic() local
833 vec4_instruction *inst; in emit_find_msb_using_lzd() local
1114 vec4_instruction *inst; nir_emit_alu() local
1519 inst = emit(MOV(dst, brw_imm_d(~0))); nir_emit_alu() member
1567 vec4_instruction *inst = emit(MOV(dst_null_df(), value)); nir_emit_alu() variable
[all...] |
| H A D | brw_vec4_visitor.cpp | 66 vec4_visitor::emit(vec4_instruction *inst) in emit() argument
77 vec4_visitor::emit_before(bblock_t *block, vec4_instruction *inst, in emit_before() argument
196 vec4_instruction *inst; IF() local
211 vec4_instruction *inst; IF() local
232 vec4_instruction *inst; CMP() local
258 vec4_instruction *inst; SCRATCH_READ() local
272 vec4_instruction *inst; SCRATCH_WRITE() local
523 vec4_instruction *inst = emit(MOV(saturated, src0)); emit_pack_unorm_4x8() local
722 vec4_instruction *inst = emit(BRW_OPCODE_SEL, dst, src0, src1); emit_minmax() local
882 vec4_instruction *inst; emit_psiz_and_flags() local
1060 vec4_instruction *inst = emit_urb_write_opcode(complete); emit_vertex() local
1069 get_scratch_offset(bblock_t *block, vec4_instruction *inst, src_reg *reladdr, int reg_offset) get_scratch_offset() argument
1114 emit_scratch_read(bblock_t *block, vec4_instruction *inst, dst_reg temp, src_reg orig_src, int base_offset) emit_scratch_read() argument
1144 emit_scratch_write(bblock_t *block, vec4_instruction *inst, int base_offset) emit_scratch_write() argument
1234 emit_resolve_reladdr(int scratch_loc[], bblock_t *block, vec4_instruction *inst, src_reg src) emit_resolve_reladdr() argument
[all...] |
| H A D | brw_vec4_generator.cpp | 32 generate_math1_gfx4(struct brw_codegen *p, vec4_instruction *inst, struct brw_reg dst, struct brw_reg src) generate_math1_gfx4() argument
55 generate_math_gfx6(struct brw_codegen *p, vec4_instruction *inst, struct brw_reg dst, struct brw_reg src0, struct brw_reg src1) generate_math_gfx6() argument
74 generate_math2_gfx4(struct brw_codegen *p, vec4_instruction *inst, struct brw_reg dst, struct brw_reg src0, struct brw_reg src1) generate_math2_gfx4() argument
108 generate_tex(struct brw_codegen *p, struct brw_vue_prog_data *prog_data, gl_shader_stage stage, vec4_instruction *inst, struct brw_reg dst, struct brw_reg src, struct brw_reg surface_index, struct brw_reg sampler_index) generate_tex() argument
338 generate_vs_urb_write(struct brw_codegen *p, vec4_instruction *inst) generate_vs_urb_write() argument
352 generate_gs_urb_write(struct brw_codegen *p, vec4_instruction *inst) generate_gs_urb_write() argument
367 generate_gs_urb_write_allocate(struct brw_codegen *p, vec4_instruction *inst) generate_gs_urb_write_allocate() argument
392 generate_gs_thread_end(struct brw_codegen *p, vec4_instruction *inst) generate_gs_thread_end() argument
480 generate_gs_svb_write(struct brw_codegen *p, vec4_instruction *inst, struct brw_reg dst, struct brw_reg src0, struct brw_reg src1) generate_gs_svb_write() argument
522 generate_gs_svb_set_destination_index(struct brw_codegen *p, vec4_instruction *inst, struct brw_reg dst, struct brw_reg src) generate_gs_svb_set_destination_index() argument
670 generate_gs_ff_sync(struct brw_codegen *p, vec4_instruction *inst, struct brw_reg dst, struct brw_reg src0, struct brw_reg src1) generate_gs_ff_sync() argument
761 generate_tcs_urb_write(struct brw_codegen *p, vec4_instruction *inst, struct brw_reg urb_header) generate_tcs_urb_write() argument
944 generate_vec4_urb_read(struct brw_codegen *p, vec4_instruction *inst, struct brw_reg dst, struct brw_reg header) generate_vec4_urb_read() argument
1005 generate_tcs_thread_end(struct brw_codegen *p, vec4_instruction *inst) generate_tcs_thread_end() argument
1139 generate_scratch_read(struct brw_codegen *p, vec4_instruction *inst, struct brw_reg dst, struct brw_reg index) generate_scratch_read() argument
1184 generate_scratch_write(struct brw_codegen *p, vec4_instruction *inst, struct brw_reg dst, struct brw_reg src, struct brw_reg index) generate_scratch_write() argument
1261 generate_pull_constant_load(struct brw_codegen *p, vec4_instruction *inst, struct brw_reg dst, struct brw_reg index, struct brw_reg offset) generate_pull_constant_load() argument
1322 generate_get_buffer_size(struct brw_codegen *p, vec4_instruction *inst, struct brw_reg dst, struct brw_reg src, struct brw_reg surf_index) generate_get_buffer_size() argument
1347 generate_pull_constant_load_gfx7(struct brw_codegen *p, vec4_instruction *inst, struct brw_reg dst, struct brw_reg surf_index, struct brw_reg offset) generate_pull_constant_load_gfx7() argument
[all...] |
| H A D | brw_eu_compact.c | 1682 has_immediate(const struct intel_device_info *devinfo, const brw_inst *inst, in has_immediate() argument
1701 precompact(const struct brw_isa_info *isa, brw_inst inst) in precompact() argument
2520 brw_inst inst = precompact(p->isa, *src); brw_compact_instructions() local
[all...] |
| H A D | brw_eu_validate.c | 93 inst_is_send(const struct brw_isa_info *isa, const brw_inst *inst) in inst_is_send() argument
107 inst_is_split_send(const struct brw_isa_info *isa, const brw_inst *inst) in inst_is_split_send() argument
137 inst_dst_type(const struct brw_isa_info *isa, const brw_inst *inst) in inst_dst_type() argument
146 inst_is_raw_move(const struct brw_isa_info *isa, const brw_inst *inst) in inst_is_raw_move() argument
171 dst_is_null(const struct intel_device_info *devinfo, const brw_inst *inst) dst_is_null() argument
178 src0_is_null(const struct intel_device_info *devinfo, const brw_inst *inst) src0_is_null() argument
186 src1_is_null(const struct intel_device_info *devinfo, const brw_inst *inst) src1_is_null() argument
193 src0_is_acc(const struct intel_device_info *devinfo, const brw_inst *inst) src0_is_acc() argument
200 src1_is_acc(const struct intel_device_info *devinfo, const brw_inst *inst) src1_is_acc() argument
207 src0_has_scalar_region(const struct intel_device_info *devinfo, const brw_inst *inst) src0_has_scalar_region() argument
216 src1_has_scalar_region(const struct intel_device_info *devinfo, const brw_inst *inst) src1_has_scalar_region() argument
225 num_sources_from_inst(const struct brw_isa_info *isa, const brw_inst *inst) num_sources_from_inst() argument
281 invalid_values(const struct brw_isa_info *isa, const brw_inst *inst) invalid_values() argument
353 sources_not_null(const struct brw_isa_info *isa, const brw_inst *inst) sources_not_null() argument
382 alignment_supported(const struct brw_isa_info *isa, const brw_inst *inst) alignment_supported() argument
395 inst_uses_src_acc(const struct brw_isa_info *isa, const brw_inst *inst) inst_uses_src_acc() argument
418 send_restrictions(const struct brw_isa_info *isa, const brw_inst *inst) send_restrictions() argument
488 is_unsupported_inst(const struct brw_isa_info *isa, const brw_inst *inst) is_unsupported_inst() argument
541 execution_type(const struct brw_isa_info *isa, const brw_inst *inst) execution_type() argument
639 is_half_float_conversion(const struct brw_isa_info *isa, const brw_inst *inst) is_half_float_conversion() argument
666 is_mixed_float(const struct brw_isa_info *isa, const brw_inst *inst) is_mixed_float() argument
703 is_byte_conversion(const struct brw_isa_info *isa, const brw_inst *inst) is_byte_conversion() argument
730 general_restrictions_based_on_operand_types(const struct brw_isa_info *isa, const brw_inst *inst) general_restrictions_based_on_operand_types() argument
1015 general_restrictions_on_region_parameters(const struct brw_isa_info *isa, const brw_inst *inst) general_restrictions_on_region_parameters() argument
1176 special_restrictions_for_mixed_float_mode(const struct brw_isa_info *isa, const brw_inst *inst) special_restrictions_for_mixed_float_mode() argument
1459 region_alignment_rules(const struct brw_isa_info *isa, const brw_inst *inst) region_alignment_rules() argument
1774 vector_immediate_restrictions(const struct brw_isa_info *isa, const brw_inst *inst) vector_immediate_restrictions() argument
1837 special_requirements_for_handling_double_precision_data_types( const struct brw_isa_info *isa, const brw_inst *inst) special_requirements_for_handling_double_precision_data_types() argument
2070 instruction_restrictions(const struct brw_isa_info *isa, const brw_inst *inst) instruction_restrictions() argument
2176 send_descriptor_restrictions(const struct brw_isa_info *isa, const brw_inst *inst) send_descriptor_restrictions() argument
2293 brw_validate_instruction(const struct brw_isa_info *isa, const brw_inst *inst, int offset, unsigned inst_size, struct disasm_info *disasm) brw_validate_instruction() argument
2337 const brw_inst *inst = assembly + src_offset; brw_validate_instructions() local
[all...] |
| /third_party/mesa3d/src/gallium/frontends/clover/spirv/ |
| H A D | invocation.cpp | 163 const auto inst = &source[i * sizeof(uint32_t)]; in create_binary_from_spirv() local
[all...] |
| /third_party/mesa3d/src/gallium/drivers/vc4/ |
| H A D | vc4_qpu_schedule.c | 49 struct queued_qpu_inst *inst; member
133 qpu_writes_r4(uint64_t inst) in qpu_writes_r4() argument
204 reads_uniform(uint64_t inst) in reads_uniform() argument
229 uint64_t inst = n->inst->inst; process_waddr_deps() local
325 uint64_t inst = n->inst->inst; calculate_deps() local
454 reads_too_soon_after_write(struct choose_scoreboard *scoreboard, uint64_t inst) reads_too_soon_after_write() argument
511 pixel_scoreboard_too_soon(struct choose_scoreboard *scoreboard, uint64_t inst) pixel_scoreboard_too_soon() argument
517 get_instruction_priority(uint64_t inst) get_instruction_priority() argument
571 uint64_t inst = n->inst->inst; choose_instruction_to_schedule() local
657 update_scoreboard_for_chosen(struct choose_scoreboard *scoreboard, uint64_t inst) update_scoreboard_for_chosen() argument
826 emit_thrsw(struct vc4_compile *c, struct choose_scoreboard *scoreboard, uint64_t inst) emit_thrsw() argument
887 uint64_t inst = chosen ? chosen->inst->inst : qpu_NOP(); schedule_instructions() local
999 struct queued_qpu_inst *inst = qpu_schedule_instructions_block() local
[all...] |
| /third_party/mesa3d/src/intel/tools/ |
| H A D | aubinator_viewer_decoder.cpp | 161 handle_state_base_address(struct aub_viewer_decode_ctx *ctx, struct intel_group *inst, const uint32_t *p) handle_state_base_address() argument
289 handle_media_interface_descriptor_load(struct aub_viewer_decode_ctx *ctx, struct intel_group *inst, const uint32_t *p) handle_media_interface_descriptor_load() argument
353 handle_3dstate_vertex_buffers(struct aub_viewer_decode_ctx *ctx, struct intel_group *inst, const uint32_t *p) handle_3dstate_vertex_buffers() argument
418 handle_3dstate_index_buffer(struct aub_viewer_decode_ctx *ctx, struct intel_group *inst, const uint32_t *p) handle_3dstate_index_buffer() argument
465 decode_single_ksp(struct aub_viewer_decode_ctx *ctx, struct intel_group *inst, const uint32_t *p) decode_single_ksp() argument
505 decode_ps_kernels(struct aub_viewer_decode_ctx *ctx, struct intel_group *inst, const uint32_t *p) decode_ps_kernels() argument
552 decode_3dstate_constant(struct aub_viewer_decode_ctx *ctx, struct intel_group *inst, const uint32_t *p) decode_3dstate_constant() argument
605 decode_3dstate_binding_table_pointers(struct aub_viewer_decode_ctx *ctx, struct intel_group *inst, const uint32_t *p) decode_3dstate_binding_table_pointers() argument
613 decode_3dstate_sampler_state_pointers(struct aub_viewer_decode_ctx *ctx, struct intel_group *inst, const uint32_t *p) decode_3dstate_sampler_state_pointers() argument
621 decode_3dstate_sampler_state_pointers_gfx6(struct aub_viewer_decode_ctx *ctx, struct intel_group *inst, const uint32_t *p) decode_3dstate_sampler_state_pointers_gfx6() argument
641 decode_dynamic_state_pointers(struct aub_viewer_decode_ctx *ctx, struct intel_group *inst, const uint32_t *p, const char *struct_type, int count) decode_dynamic_state_pointers() argument
693 decode_3dstate_viewport_state_pointers_cc(struct aub_viewer_decode_ctx *ctx, struct intel_group *inst, const uint32_t *p) decode_3dstate_viewport_state_pointers_cc() argument
701 decode_3dstate_viewport_state_pointers_sf_clip(struct aub_viewer_decode_ctx *ctx, struct intel_group *inst, const uint32_t *p) decode_3dstate_viewport_state_pointers_sf_clip() argument
709 decode_3dstate_blend_state_pointers(struct aub_viewer_decode_ctx *ctx, struct intel_group *inst, const uint32_t *p) decode_3dstate_blend_state_pointers() argument
717 decode_3dstate_cc_state_pointers(struct aub_viewer_decode_ctx *ctx, struct intel_group *inst, const uint32_t *p) decode_3dstate_cc_state_pointers() argument
725 decode_3dstate_scissor_state_pointers(struct aub_viewer_decode_ctx *ctx, struct intel_group *inst, const uint32_t *p) decode_3dstate_scissor_state_pointers() argument
733 decode_load_register_imm(struct aub_viewer_decode_ctx *ctx, struct intel_group *inst, const uint32_t *p) decode_load_register_imm() argument
749 decode_3dprimitive(struct aub_viewer_decode_ctx *ctx, struct intel_group *inst, const uint32_t *p) decode_3dprimitive() argument
760 handle_urb(struct aub_viewer_decode_ctx *ctx, struct intel_group *inst, const uint32_t *p) handle_urb() argument
783 handle_urb_read(struct aub_viewer_decode_ctx *ctx, struct intel_group *inst, const uint32_t *p) handle_urb_read() argument
807 handle_urb_constant(struct aub_viewer_decode_ctx *ctx, struct intel_group *inst, const uint32_t *p) handle_urb_constant() argument
901 struct intel_group *inst; aub_viewer_render_batch() local
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| /third_party/mesa3d/src/gallium/drivers/radeonsi/ |
| H A D | si_debug.c | 863 struct si_shader_inst *inst = &instructions[(*num)++]; in si_add_split_disasm() local
939 struct si_shader_inst *inst = &instructions[i]; in si_print_annotated_shader() local
[all...] |
| /third_party/mesa3d/src/gallium/auxiliary/tgsi/ |
| H A D | tgsi_text.c | 1044 struct tgsi_full_instruction inst; in parse_instruction() local
[all...] |
| /third_party/mesa3d/src/gallium/drivers/etnaviv/ |
| H A D | etnaviv_compiler_nir.c | 1196 struct etna_inst *inst = &c->code[i]; in etna_compile_shader() local
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| /third_party/mesa3d/src/gallium/drivers/r300/compiler/ |
| H A D | radeon_code.h | 192 uint32_t inst[R400_PFS_MAX_TEX_INST]; member
203 } inst[R400_PFS_MAX_ALU_INST]; member
225 } inst[R500_PFS_MAX_INST]; member
|