| /kernel/linux/linux-5.10/arch/riscv/kernel/ |
| H A D | module.c | 78 u16 imm5 = (offset & 0x20) >> (5 - 2); in apply_r_riscv_rcv_branch_rela() local
96 u16 imm5 = (offset & 0x20) >> (5 - 2); in apply_r_riscv_rvc_jump_rela() local
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| /kernel/linux/linux-5.10/arch/arm/probes/kprobes/ |
| H A D | actions-thumb.c | 372 long imm5 = insn & 0xf8; in t16_simulate_cbz() local
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| /kernel/linux/linux-6.6/arch/arm/probes/kprobes/ |
| H A D | actions-thumb.c | 372 long imm5 = insn & 0xf8; in t16_simulate_cbz() local
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| /kernel/linux/linux-6.6/arch/riscv/kernel/ |
| H A D | module.c | 79 u16 imm5 = (offset & 0x20) >> (5 - 2); in apply_r_riscv_rvc_branch_rela() local
97 u16 imm5 = (offset & 0x20) >> (5 - 2); in apply_r_riscv_rvc_jump_rela() local
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| /third_party/node/deps/v8/src/diagnostics/arm64/ |
| H A D | disasm-arm64.cc | 3981 unsigned imm5 = instr->ImmNEON5(); in SubstituteImmediateField() local
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| /third_party/node/deps/v8/src/codegen/mips64/ |
| H A D | assembler-mips64.cc | 1198 GenInstrMsaI5(SecondaryField operation, SecondaryField df, int32_t imm5, MSARegister ws, MSARegister wd) GenInstrMsaI5() argument
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| /third_party/node/deps/v8/src/codegen/mips/ |
| H A D | assembler-mips.cc | 1269 GenInstrMsaI5(SecondaryField operation, SecondaryField df, int32_t imm5, MSARegister ws, MSARegister wd) GenInstrMsaI5() argument
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| /third_party/node/deps/v8/src/codegen/arm/ |
| H A D | assembler-arm.cc | 3121 int imm5 = 32 - fraction_bits; in vcvt_f64_s32() local
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| /third_party/node/deps/v8/src/codegen/riscv64/ |
| H A D | assembler-riscv64.cc | 1219 void Assembler::GenInstrV(uint8_t funct6, VRegister vd, int8_t imm5, in GenInstrV() argument
1719 void Assembler::csrrwi(Register rd, ControlStatusReg csr, uint8_t imm5) { in csrrwi() argument
1723 void Assembler::csrrsi(Register rd, ControlStatusReg csr, uint8_t imm5) { in csrrsi() argument
1321 GenInstrCSR_ii(uint8_t funct3, Register rd, ControlStatusReg csr, uint8_t imm5) GenInstrCSR_ii() argument
1727 csrrci(Register rd, ControlStatusReg csr, uint8_t imm5) csrrci() argument
2524 vmerge_vi(VRegister vd, uint8_t imm5, VRegister vs2) vmerge_vi() argument
2536 vadc_vi(VRegister vd, uint8_t imm5, VRegister vs2) vadc_vi() argument
2548 vmadc_vi(VRegister vd, uint8_t imm5, VRegister vs2) vmadc_vi() argument
2559 vrgather_vi(VRegister vd, VRegister vs2, int8_t imm5, MaskType mask) vrgather_vi() argument
[all...] |
| /third_party/vixl/src/aarch64/ |
| H A D | assembler-sve-aarch64.cc | 2228 void Assembler::index(const ZRegister& zd, const Register& rn, int imm5) { in index() argument
2240 void Assembler::index(const ZRegister& zd, int imm5, const Register& rm) { in index() argument
2812 cmpeq(const PRegisterWithLaneSize& pd, const PRegisterZ& pg, const ZRegister& zn, int imm5) cmpeq() argument
2827 cmpge(const PRegisterWithLaneSize& pd, const PRegisterZ& pg, const ZRegister& zn, int imm5) cmpge() argument
2842 cmpgt(const PRegisterWithLaneSize& pd, const PRegisterZ& pg, const ZRegister& zn, int imm5) cmpgt() argument
2857 cmple(const PRegisterWithLaneSize& pd, const PRegisterZ& pg, const ZRegister& zn, int imm5) cmple() argument
2872 cmplt(const PRegisterWithLaneSize& pd, const PRegisterZ& pg, const ZRegister& zn, int imm5) cmplt() argument
2887 cmpne(const PRegisterWithLaneSize& pd, const PRegisterZ& pg, const ZRegister& zn, int imm5) cmpne() argument
4268 ldff1b(const ZRegister& zt, const PRegisterZ& pg, const ZRegister& zn, int imm5) ldff1b() argument
4301 ldff1d(const ZRegister& zt, const PRegisterZ& pg, const ZRegister& zn, int imm5) ldff1d() argument
4337 ldff1h(const ZRegister& zt, const PRegisterZ& pg, const ZRegister& zn, int imm5) ldff1h() argument
4371 ldff1sb(const ZRegister& zt, const PRegisterZ& pg, const ZRegister& zn, int imm5) ldff1sb() argument
4408 ldff1sh(const ZRegister& zt, const PRegisterZ& pg, const ZRegister& zn, int imm5) ldff1sh() argument
4442 ldff1sw(const ZRegister& zt, const PRegisterZ& pg, const ZRegister& zn, int imm5) ldff1sw() argument
4479 ldff1w(const ZRegister& zt, const PRegisterZ& pg, const ZRegister& zn, int imm5) ldff1w() argument
4525 int64_t imm5 = addr.GetImmediateOffset(); SVEGatherPrefetchVectorPlusImmediateHelper() local
[all...] |
| H A D | disasm-aarch64.cc | 6820 unsigned imm5 = instr->GetImmNEON5(); in Disassembler() local
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| H A D | macro-assembler-aarch64.h | 3919 int imm5; in Cmpeq() local
3940 int imm5; in Cmpge() local
3961 int imm5; in Cmpgt() local
4021 int imm5; in Cmple() local
4080 int imm5; Cmplt() local
4101 int imm5; Cmpne() local
5232 Ldff1b(const ZRegister& zt, const PRegisterZ& pg, const ZRegister& zn, int imm5) Ldff1b() argument
5248 Ldff1d(const ZRegister& zt, const PRegisterZ& pg, const ZRegister& zn, int imm5) Ldff1d() argument
5264 Ldff1h(const ZRegister& zt, const PRegisterZ& pg, const ZRegister& zn, int imm5) Ldff1h() argument
5280 Ldff1sb(const ZRegister& zt, const PRegisterZ& pg, const ZRegister& zn, int imm5) Ldff1sb() argument
5296 Ldff1sh(const ZRegister& zt, const PRegisterZ& pg, const ZRegister& zn, int imm5) Ldff1sh() argument
5312 Ldff1sw(const ZRegister& zt, const PRegisterZ& pg, const ZRegister& zn, int imm5) Ldff1sw() argument
5328 Ldff1w(const ZRegister& zt, const PRegisterZ& pg, const ZRegister& zn, int imm5) Ldff1w() argument
[all...] |
| H A D | simulator-aarch64.cc | 8174 int imm5 = instr->GetImmNEON5(); in Simulator() local
9240 int imm5 = instr->GetImmNEON5(); in Simulator() local
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