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Searched defs:devinfo (Results 76 - 100 of 205) sorted by relevance

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/third_party/mesa3d/src/intel/compiler/
H A Dtest_vec4_cmod_propagation.cpp40 struct intel_device_info *devinfo; member in cmod_propagation_vec4_test
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H A Dbrw_vec4_tcs.cpp358 const struct intel_device_info *devinfo = compiler->devinfo; in brw_compile_tcs() local
H A Dbrw_fs_copy_propagation.cpp375 const struct intel_device_info *devinfo = compiler->devinfo; in can_take_stride() local
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H A Dbrw_fs_combine_constants.cpp49 could_coissue(const struct intel_device_info *devinfo, const fs_inst *inst) in could_coissue() argument
76 must_promote_imm(const struct intel_device_info *devinfo, const fs_inst *inst) in must_promote_imm() argument
215 get_constant_value(const struct intel_device_info *devinfo, in get_constant_value() argument
363 supports_src_as_imm(const struct intel_device_info *devinfo, enum opcode op) in supports_src_as_imm() argument
376 can_promote_src_as_imm(const struct intel_device_info *devinfo, fs_inst *inst, unsigned src_idx) can_promote_src_as_imm() argument
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H A Dbrw_fs_scoreboard.cpp74 inferred_sync_pipe(const struct intel_device_info *devinfo, const fs_inst *inst) in inferred_sync_pipe() argument
106 inferred_exec_pipe(const struct intel_device_info *devinfo, const fs_inst *inst) in inferred_exec_pipe() argument
152 ordered_unit(const struct intel_device_info *devinfo, const fs_inst *inst, in ordered_unit() argument
390 assert(from < n); if (is[from] != from) assign(is[from], to); is[from] = to; } } unsigned *is; unsigned n; }; struct dependency { dependency() : ordered(TGL_REGDIST_NULL), jp(), unordered(TGL_SBID_NULL), id(0), exec_all(false) {} dependency(tgl_regdist_mode mode, const ordered_address &jp, bool exec_all) : ordered(mode), jp(jp), unordered(TGL_SBID_NULL), id(0), exec_all(exec_all) {} dependency(tgl_sbid_mode mode, unsigned id, bool exec_all) : ordered(TGL_REGDIST_NULL), jp(), unordered(mode), id(id), exec_all(exec_all) {} tgl_regdist_mode ordered; ordered_address jp; tgl_sbid_mode unordered; unsigned id; bool exec_all; static const dependency done; friend bool operator==(const dependency &dep0, const dependency &dep1) { return dep0.ordered == dep1.ordered && dep0.jp == dep1.jp && dep0.unordered == dep1.unordered && dep0.id == dep1.id && dep0.exec_all == dep1.exec_all; } friend bool operator!=(const dependency &dep0, const dependency &dep1) { return !(dep0 == dep1); } }; const dependency dependency::done = dependency(TGL_REGDIST_DST, ordered_address(), false); bool is_valid(const dependency &dep) { return dep.ordered || dep.unordered; } dependency merge(equivalence_relation &eq, const dependency &dep0, const dependency &dep1) { dependency dep; if (dep0.ordered || dep1.ordered) { dep.ordered = dep0.ordered | dep1.ordered; for (unsigned p = 0; p < IDX(TGL_PIPE_ALL); p++) dep.jp.jp[p] = MAX2(dep0.jp.jp[p], dep1.jp.jp[p]); } if (dep0.unordered || dep1.unordered) { dep.unordered = dep0.unordered | dep1.unordered; dep.id = eq.link(dep0.unordered ? dep0.id : dep1.id, dep1.unordered ? dep1.id : dep0.id); } dep.exec_all = dep0.exec_all || dep1.exec_all; return dep; } dependency shadow(const dependency &dep0, const dependency &dep1) { if (dep0.ordered == TGL_REGDIST_SRC && is_valid(dep1) && !(dep1.unordered & TGL_SBID_DST) && !(dep1.ordered & TGL_REGDIST_DST)) { dependency dep = dep1; dep.ordered |= dep0.ordered; for (unsigned p = 0; p < IDX(TGL_PIPE_ALL); p++) dep.jp.jp[p] = MAX2(dep.jp.jp[p], dep0.jp.jp[p]); return dep; } else { return is_valid(dep1) ? dep1 : dep0; } } dependency transport(dependency dep, int delta[IDX(TGL_PIPE_ALL)]) { if (dep.ordered) { for (unsigned p = 0; p < IDX(TGL_PIPE_ALL); p++) { if (dep.jp.jp[p] > INT_MIN) dep.jp.jp[p] += delta[p]; } } return dep; } dependency dependency_for_read(dependency dep) { dep.ordered &= TGL_REGDIST_DST; return dep; } dependency dependency_for_write(const struct intel_device_info *devinfo, const fs_inst *inst, dependency dep) { if (!is_unordered(inst) && is_single_pipe(dep.jp, inferred_exec_pipe(devinfo, inst))) dep.ordered &= TGL_REGDIST_DST; return dep; } class scoreboard { public: dependency get(const fs_reg &r) const { if (const dependency *p = const_cast<scoreboard *>(this)->dep(r)) return *p; else return dependency(); } void set(const fs_reg &r, const dependency &d) { if (dependency *p = dep(r)) *p = d; } friend scoreboard merge(equivalence_relation &eq, const scoreboard &sb0, const scoreboard &sb1) { scoreboard sb; for (unsigned i = 0; i < ARRAY_SIZE(sb.grf_deps); i++) sb.grf_deps[i] = merge(eq, sb0.grf_deps[i], sb1.grf_deps[i]); sb.addr_dep = merge(eq, sb0.addr_dep, sb1.addr_dep); sb.accum_dep = merge(eq, sb0.accum_dep, sb1.accum_dep); return sb; } friend scoreboard shadow(const scoreboard &sb0, const scoreboard &sb1) { scoreboard sb; for (unsigned i = 0; i < ARRAY_SIZE(sb.grf_deps); i++) sb.grf_deps[i] = shadow(sb0.grf_deps[i], sb1.grf_deps[i]); sb.addr_dep = shadow(sb0.addr_dep, sb1.addr_dep); sb.accum_dep = shadow(sb0.accum_dep, sb1.accum_dep); return sb; } friend scoreboard transport(const scoreboard &sb0, int delta[IDX(TGL_PIPE_ALL)]) { scoreboard sb; for (unsigned i = 0; i < ARRAY_SIZE(sb.grf_deps); i++) sb.grf_deps[i] = transport(sb0.grf_deps[i], delta); sb.addr_dep = transport(sb0.addr_dep, delta); sb.accum_dep = transport(sb0.accum_dep, delta); return sb; } friend bool operator==(const scoreboard &sb0, const scoreboard &sb1) { for (unsigned i = 0; i < ARRAY_SIZE(sb0.grf_deps); i++) { if (sb0.grf_deps[i] != sb1.grf_deps[i]) return false; } if (sb0.addr_dep != sb1.addr_dep) return false; if (sb0.accum_dep != sb1.accum_dep) return false; return true; } friend bool operator!=(const scoreboard &sb0, const scoreboard &sb1) { return !(sb0 == sb1); } private: dependency grf_deps[BRW_MAX_GRF]; dependency addr_dep; dependency accum_dep; dependency * dep(const fs_reg &r) { const unsigned reg = (r.file == VGRF ? r.nr + r.offset / REG_SIZE : reg_offset(r) / REG_SIZE); return (r.file == VGRF || r.file == FIXED_GRF ? &grf_deps[reg] : r.file == MRF ? &grf_deps[GFX7_MRF_HACK_START + reg] : r.file == ARF && reg >= BRW_ARF_ADDRESS && reg < BRW_ARF_ACCUMULATOR ? &addr_dep : r.file == ARF && reg >= BRW_ARF_ACCUMULATOR && reg < BRW_ARF_FLAG ? &accum_dep : NULL); } }; struct dependency_list { dependency_list() : deps(NULL), n(0) {} ~dependency_list() { free(deps); } void push_back(const dependency &dep) { deps = (dependency *)realloc(deps, (n + 1) * sizeof(*deps)); deps[n++] = dep; } unsigned size() const { return n; } const dependency & operator[](unsigned i) const { assert(i < n); return deps[i]; } dependency & operator[](unsigned i) { assert(i < n); return deps[i]; } private: dependency_list(const dependency_list &); dependency_list & operator=(const dependency_list &); dependency *deps; unsigned n; }; void add_dependency(const unsigned *ids, dependency_list &deps, dependency dep) { if (is_valid(dep)) { if (dep.unordered) dep.id = ids[dep.id]; for (unsigned i = 0; i < deps.size(); i++) { if (deps[i].exec_all != dep.exec_all && (!deps[i].exec_all || (dep.unordered & TGL_SBID_SET)) && (!dep.exec_all || (deps[i].unordered & TGL_SBID_SET))) continue; if (dep.ordered && deps[i].ordered) { for (unsigned p = 0; p < IDX(TGL_PIPE_ALL); p++) deps[i].jp.jp[p] = MAX2(deps[i].jp.jp[p], dep.jp.jp[p]); deps[i].ordered |= dep.ordered; deps[i].exec_all |= dep.exec_all; dep.ordered = TGL_REGDIST_NULL; } if (dep.unordered && deps[i].unordered && deps[i].id == dep.id) { deps[i].unordered |= dep.unordered; deps[i].exec_all |= dep.exec_all; dep.unordered = TGL_SBID_NULL; } } if (is_valid(dep)) deps.push_back(dep); } } tgl_swsb ordered_dependency_swsb(const dependency_list &deps, const ordered_address &jp, bool exec_all) { tgl_pipe p = TGL_PIPE_NONE; unsigned min_dist = ~0u; for (unsigned i = 0; i < deps.size(); i++) { if (deps[i].ordered && exec_all >= deps[i].exec_all) { for (unsigned q = 0; q < IDX(TGL_PIPE_ALL); q++) { const unsigned dist = jp.jp[q] - int64_t(deps[i].jp.jp[q]); const unsigned max_dist = (q == IDX(TGL_PIPE_LONG) ? 14 : 10); assert(jp.jp[q] > deps[i].jp.jp[q]); if (dist <= max_dist) { p = (p && IDX(p) != q ? TGL_PIPE_ALL : tgl_pipe(TGL_PIPE_FLOAT + q)); min_dist = MIN3(min_dist, dist, 7); } } } } return { p ? min_dist : 0, p }; } bool find_ordered_dependency(const dependency_list &deps, const ordered_address &jp, bool exec_all) { return ordered_dependency_swsb(deps, jp, exec_all).regdist; } tgl_sbid_mode find_unordered_dependency(const dependency_list &deps, tgl_sbid_mode unordered, bool exec_all) { if (unordered) { for (unsigned i = 0; i < deps.size(); i++) { if ((unordered & deps[i].unordered) && exec_all >= deps[i].exec_all) return deps[i].unordered; } } return TGL_SBID_NULL; } tgl_sbid_mode baked_unordered_dependency_mode(const struct intel_device_info *devinfo, const fs_inst *inst, const dependency_list &deps, const ordered_address &jp) { const bool exec_all = inst->force_writemask_all; const bool has_ordered = find_ordered_dependency(deps, jp, exec_all); const tgl_pipe ordered_pipe = ordered_dependency_swsb(deps, jp, exec_all).pipe; if (find_unordered_dependency(deps, TGL_SBID_SET, exec_all)) return find_unordered_dependency(deps, TGL_SBID_SET, exec_all); else if (has_ordered && is_unordered(inst)) return TGL_SBID_NULL; else if (find_unordered_dependency(deps, TGL_SBID_DST, exec_all) && (!has_ordered || ordered_pipe == inferred_sync_pipe(devinfo, inst))) return find_unordered_dependency(deps, TGL_SBID_DST, exec_all); else if (!has_ordered) return find_unordered_dependency(deps, TGL_SBID_SRC, exec_all); else return TGL_SBID_NULL; } bool baked_ordered_dependency_mode(const struct intel_device_info *devinfo, const fs_inst *inst, const dependency_list &deps, const ordered_address &jp) { const bool exec_all = inst->force_writemask_all; const bool has_ordered = find_ordered_dependency(deps, jp, exec_all); const tgl_pipe ordered_pipe = ordered_dependency_swsb(deps, jp, exec_all).pipe; const tgl_sbid_mode unordered_mode = baked_unordered_dependency_mode(devinfo, inst, deps, jp); if (!has_ordered) return false; else if (!unordered_mode) return true; else return ordered_pipe == inferred_sync_pipe(devinfo, inst) && unordered_mode == (is_unordered(inst) ? TGL_SBID_SET : TGL_SBID_DST); } void update_inst_scoreboard(const fs_visitor *shader, const ordered_address *jps, const fs_inst *inst, unsigned ip, scoreboard &sb) { const bool exec_all = inst->force_writemask_all; const struct intel_device_info *devinfo = shader->devinfo; const tgl_pipe p = inferred_exec_pipe(devinfo, inst); const ordered_address jp = p ? ordered_address(p, jps[ip].jp[IDX(p)]) : ordered_address(); const bool is_ordered = ordered_unit(devinfo, inst, IDX(TGL_PIPE_ALL)); for (unsigned i = 0; i < inst->sources; i++) { const dependency rd_dep = (inst->is_payload(i) || inst->is_math()) ? dependency(TGL_SBID_SRC, ip, exec_all) : is_ordered ? dependency(TGL_REGDIST_SRC, jp, exec_all) : dependency::done; for (unsigned j = 0; j < regs_read(inst, i); j++) { const fs_reg r = byte_offset(inst->src[i], REG_SIZE * j); sb.set(r, shadow(sb.get(r), rd_dep)); } } if (inst->reads_accumulator_implicitly()) sb.set(brw_acc_reg(8), dependency(TGL_REGDIST_SRC, jp, exec_all)); if (is_send(inst) && inst->base_mrf != -1) { const dependency rd_dep = dependency(TGL_SBID_SRC, ip, exec_all); for (unsigned j = 0; j < inst->mlen; j++) sb.set(brw_uvec_mrf(8, inst->base_mrf + j, 0), rd_dep); } const dependency wr_dep = is_unordered(inst) ? dependency(TGL_SBID_DST, ip, exec_all) : is_ordered ? dependency(TGL_REGDIST_DST, jp, exec_all) : dependency(); if (inst->writes_accumulator_implicitly(devinfo)) sb.set(brw_acc_reg(8), wr_dep); if (is_valid(wr_dep) && inst->dst.file != BAD_FILE && !inst->dst.is_null()) assign() argument
1122 const struct intel_device_info *devinfo = shader->devinfo; gather_inst_dependencies() local
1253 const struct intel_device_info *devinfo = shader->devinfo; emit_inst_dependencies() local
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/third_party/mesa3d/src/intel/vulkan/
H A Danv_perf.c39 const struct intel_device_info *devinfo = &device->info; in anv_physical_device_init_perf() local
/third_party/mesa3d/src/intel/ds/
H A Dintel_driver_ds.cc517 intel_ds_device_init(struct intel_ds_device *device, struct intel_device_info *devinfo, int drm_fd, uint32_t gpu_id, enum intel_ds_api api) intel_ds_device_init() argument
/third_party/mesa3d/src/intel/perf/
H A Dintel_perf_mdapi.h135 intel_perf_query_mdapi_write_marker(void *data, uint32_t data_size, const struct intel_device_info *devinfo, uint64_t value) intel_perf_query_mdapi_write_marker() argument
/third_party/mesa3d/src/intel/tools/
H A Di965_asm.c107 struct intel_device_info *devinfo; in i965_disasm_init() local
218 struct intel_device_info *devinfo = NULL; main() local
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H A Daubinator_viewer.h71 const struct intel_device_info *devinfo; member
H A Dintel_noop_drm_shim.c43 struct intel_device_info devinfo; member
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/third_party/mesa3d/src/gallium/drivers/iris/
H A Diris_clear.c44 const struct intel_device_info *devinfo = &batch->screen->devinfo; in iris_is_color_fast_clear_compatible() local
171 const struct intel_device_info *devinfo = &batch->screen->devinfo; in fast_clear_color() local
318 const struct intel_device_info *devinfo = &batch->screen->devinfo; in clear_color() local
387 const struct intel_device_info *devinfo = &screen->devinfo; can_fast_clear_depth() local
680 const struct intel_device_info *devinfo = &screen->devinfo; iris_clear_texture() local
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H A Diris_draw.c69 const struct intel_device_info *devinfo = &screen->devinfo; in iris_update_draw_info() local
273 const struct intel_device_info *devinfo = &screen->devinfo; in iris_draw_vbo() local
H A Diris_context.c291 const struct intel_device_info *devinfo = &screen->devinfo; in iris_create_context() local
H A Diris_program_cache.c160 const struct intel_device_info *devinfo = &screen->devinfo; in iris_upload_shader() local
/third_party/mesa3d/src/gallium/drivers/lima/
H A Dlima_screen.c468 drmDevicePtr devinfo; in lima_screen_set_plb_max_blk() local
/third_party/mesa3d/src/intel/common/
H A Dintel_l3_config.c163 get_l3_list(const struct intel_device_info *devinfo) in get_l3_list() argument
260 intel_get_default_l3_weights(const struct intel_device_info *devinfo, in intel_get_default_l3_weights() argument
282 intel_get_default_l3_config(const struct intel_device_info *devinfo) intel_get_default_l3_config() argument
304 intel_get_l3_config(const struct intel_device_info *devinfo, struct intel_l3_weights w0) intel_get_l3_config() argument
330 get_l3_way_size(const struct intel_device_info *devinfo) get_l3_way_size() argument
345 get_urb_size_scale(const struct intel_device_info *devinfo) get_urb_size_scale() argument
351 intel_get_l3_config_urb_size(const struct intel_device_info *devinfo, const struct intel_l3_config *cfg) intel_get_l3_config_urb_size() argument
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H A Dintel_aux_map.c201 intel_aux_map_init(void *driver_ctx, struct intel_mapped_pinned_buffer_alloc *buffer_alloc, const struct intel_device_info *devinfo) intel_aux_map_init() argument
/third_party/mesa3d/src/gallium/drivers/crocus/
H A Dcrocus_draw.c82 const struct intel_device_info *devinfo = &screen->devinfo; in can_cut_index_handle_prim() local
277 const struct intel_device_info *devinfo = &batch->screen->devinfo; crocus_indirect_draw_vbo() local
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H A Dcrocus_context.c248 const struct intel_device_info *devinfo = &screen->devinfo; in crocus_create_context() local
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H A Dcrocus_screen.c111 const struct intel_device_info *devinfo = &screen->devinfo; in crocus_get_driver_uuid() local
120 const struct intel_device_info *devinfo = &screen->devinfo; in crocus_get_name() local
139 const struct intel_device_info *devinfo in crocus_get_param() local
408 const struct intel_device_info *devinfo = &screen->devinfo; crocus_get_paramf() local
452 const struct intel_device_info *devinfo = &screen->devinfo; crocus_get_shader_param() local
549 const struct intel_device_info *devinfo = &screen->devinfo; crocus_get_compute_param() local
669 crocus_get_default_l3_config(const struct intel_device_info *devinfo, bool compute) crocus_get_default_l3_config() argument
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/third_party/NuttX/drivers/usbdev/gadget/
H A Dcomposite.c398 struct usbdev_devinfo_s *devinfo; in composite_classsetup() local
/third_party/NuttX/drivers/usbdev/gadget/fconfig/src/
H A Df_config.c190 struct usbdev_devinfo_s *devinfo = &com_dev->device[i].compdesc.devinfo; in fconfig_mkstrdesc() local
/third_party/mesa3d/src/broadcom/qpu/
H A Dqpu_instr.c31 v3d_qpu_magic_waddr_name(const struct v3d_device_info *devinfo, in v3d_qpu_magic_waddr_name() argument
546 v3d_qpu_magic_waddr_is_tmu(const struct v3d_device_info *devinfo, in v3d_qpu_magic_waddr_is_tmu() argument
701 v3d_qpu_writes_tmu(const struct v3d_device_info *devinfo, in v3d_qpu_writes_tmu() argument
712 v3d_qpu_writes_tmu_not_tmuc(const struct v3d_device_info *devinfo, in v3d_qpu_writes_tmu_not_tmuc() argument
758 v3d_qpu_writes_unifa(const struct v3d_device_info *devinfo, in v3d_qpu_writes_unifa() argument
803 qpu_writes_magic_waddr_explicitly(const struct v3d_device_info *devinfo, const struct v3d_qpu_instr *inst, uint32_t waddr) qpu_writes_magic_waddr_explicitly() argument
824 v3d_qpu_writes_r3(const struct v3d_device_info *devinfo, const struct v3d_qpu_instr *inst) v3d_qpu_writes_r3() argument
834 v3d_qpu_writes_r4(const struct v3d_device_info *devinfo, const struct v3d_qpu_instr *inst) v3d_qpu_writes_r4() argument
862 v3d_qpu_writes_r5(const struct v3d_device_info *devinfo, const struct v3d_qpu_instr *inst) v3d_qpu_writes_r5() argument
872 v3d_qpu_writes_accum(const struct v3d_device_info *devinfo, const struct v3d_qpu_instr *inst) v3d_qpu_writes_accum() argument
904 v3d_qpu_sig_writes_address(const struct v3d_device_info *devinfo, const struct v3d_qpu_sig *sig) v3d_qpu_sig_writes_address() argument
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/third_party/mesa3d/src/gallium/drivers/v3d/
H A Dv3dx_emit.c83 swizzled_border_color(const struct v3d_device_info *devinfo, in swizzled_border_color() argument
125 const struct v3d_device_info *devinfo = &v3d->screen->devinfo; in emit_one_texture() local

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