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Searched defs:const (Results 12251 - 12275 of 12930) sorted by relevance

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/third_party/skia/third_party/externals/swiftshader/third_party/subzero/src/
H A DIceOperand.h68 OperandKind getKind() const { return Kind; } in getKind() argument
69 Type getType() const { return Ty; } in getType() argument
74 SizeT getNumVars() const { return NumVars; } in getNumVars() argument
75 Variable *getVar(SizeT I) const { in getVar() argument
93 dump(Ostream &Str) const dump() argument
103 hashValue() const hashValue() argument
109 getExternalData() const getExternalData() argument
155 getLabelName() const getLabelName() argument
157 getShouldBePooled() const getShouldBePooled() argument
166 getLookupCount() const getLookupCount() argument
206 getValue() const getValue() argument
281 dump(const Cfg *, Ostream &Str) const dump() argument
291 dump(const Cfg *, Ostream &Str) const dump() argument
315 hasOffset() const hasOffset() argument
317 getOffset() const getOffset() argument
386 getOffset() const getOffset() argument
394 getEmitString() const getEmitString() argument
396 getName() const getName() argument
469 operator unsigned() const operator unsigned() argument
472 assertIsValid() const assertIsValid() argument
491 hasValue() const hasValue() argument
492 hasNoValue() const hasNoValue() argument
590 getWeight() const getWeight() argument
633 isEmpty() const isEmpty() argument
634 getStart() const getStart() argument
637 getEnd() const getEnd() argument
646 getNumSegments() const getNumSegments() argument
648 getSegments() const getSegments() argument
690 getIndex() const getIndex() argument
691 getName() const getName() argument
702 getIsArg() const getIsArg() argument
704 getIsImplicitArg() const getIsImplicitArg() argument
708 getIgnoreLiveness() const getIgnoreLiveness() argument
715 hasStackOffset() const hasStackOffset() argument
718 hasKnownStackOffset() const hasKnownStackOffset() argument
722 getStackOffset() const getStackOffset() argument
735 getSymbolicStackOffset() const getSymbolicStackOffset() argument
741 hasReg() const hasReg() argument
742 getRegNum() const getRegNum() argument
748 hasRegTmp() const hasRegTmp() argument
749 getRegNumTmp() const getRegNumTmp() argument
755 mustHaveReg() const mustHaveReg() argument
757 mustNotHaveReg() const mustNotHaveReg() argument
760 mayHaveReg() const mayHaveReg() argument
767 isRematerializable() const isRematerializable() argument
771 getRegClass() const getRegClass() argument
774 getLiveRange() const getLiveRange() argument
784 rangeEndsBefore(const Variable *Other) const rangeEndsBefore() argument
787 rangeOverlaps(const Variable *Other) const rangeOverlaps() argument
791 rangeOverlapsStart(const Variable *Other) const rangeOverlapsStart() argument
809 getBaseRegNum() const getBaseRegNum() argument
813 getLinkedTo() const getLinkedTo() argument
815 getLinkedToRoot() const getLinkedToRoot() argument
826 getLinkedToStackRoot() const getLinkedToStackRoot() argument
843 getExternalData() const getExternalData() argument
922 getLo() const getLo() argument
926 getHi() const getHi() argument
988 getContainers() const getContainers() argument
1047 getMultiDef() const getMultiDef() argument
1048 getMultiBlock() const getMultiBlock() argument
1052 getLatterDefinitions() const getLatterDefinitions() argument
1053 getNode() const getNode() argument
1054 getUseWeight() const getUseWeight() argument
1085 getKind() const getKind() argument
1090 isTracked(const Variable *Var) const isTracked() argument
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H A DIceTargetLoweringARM32.h47 bool hasFeature(ARM32InstructionSet I) const { return I <= InstructionSet; } in hasFeature() argument
125 getReservedTmpReg() const getReservedTmpReg() argument
171 hasCPUFeature(TargetARM32Features::ARM32InstructionSet I) const hasCPUFeature() argument
190 shAmtImm(uint32_t ShAmtImm) const shAmtImm() argument
197 getCtx() const getCtx() argument
234 invert() const invert() argument
581 createForLabelOrDuplicate(InstARM32Label *Label) const createForLabelOrDuplicate() argument
660 assertNoLabelAndReturnCond() const assertNoLabelAndReturnCond() argument
1017 assertNoTempOrAssignedToIP() const assertNoTempOrAssignedToIP() argument
1142 getProducerOf(const Operand *Opnd) const getProducerOf() argument
1156 dump(const Cfg *Func) const dump() argument
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/ProfileData/
H A DInstrProf.cpp209 std::string InstrProfError::message() const { in message() argument
481 accumulateCounts(CountSumOrPercent &Sum) const accumulateCounts() argument
1211 dump(raw_fd_ostream &OS) const dump() argument
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Support/
H A DFileCheck.cpp28 Expected<uint64_t> NumericVariableUse::eval() const { in eval() argument
36 Expected<uint64_t> BinaryOperation::eval() const { in eval() argument
54 Expected<std::string> NumericSubstitution::getResult() const { in getResult() argument
61 Expected<std::string> StringSubstitution::getResult() const { in getResult() argument
602 match(StringRef Buffer, size_t &MatchLen, const SourceMgr &SM) const match() argument
694 computeMatchDistance(StringRef Buffer) const computeMatchDistance() argument
711 printSubstitutions(const SourceMgr &SM, StringRef Buffer, SMRange MatchRange) const printSubstitutions() argument
770 printFuzzyMatch(const SourceMgr &SM, StringRef Buffer, std::vector<FileCheckDiag> *Diags) const printFuzzyMatch() argument
942 getDescription(StringRef Prefix) const getDescription() argument
1410 Check(const SourceMgr &SM, StringRef Buffer, bool IsLabelScanMode, size_t &MatchLen, FileCheckRequest &Req, std::vector<FileCheckDiag> *Diags) const Check() argument
1492 CheckNext(const SourceMgr &SM, StringRef Buffer) const CheckNext() argument
1531 CheckSame(const SourceMgr &SM, StringRef Buffer) const CheckSame() argument
1553 CheckNot(const SourceMgr &SM, StringRef Buffer, const std::vector<const Pattern *> &NotStrings, const FileCheckRequest &Req, std::vector<FileCheckDiag> *Diags) const CheckNot() argument
1579 CheckDag(const SourceMgr &SM, StringRef Buffer, std::vector<const Pattern *> &NotStrings, const FileCheckRequest &Req, std::vector<FileCheckDiag> *Diags) const CheckDag() argument
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H A DVirtualFileSystem.cpp89 bool Status::equivalent(const Status &Other) const { in equivalent() argument
94 bool Status::isDirectory() const { return Type == file_type::directory_file; } in isDirectory() argument
96 bool Status::isRegularFile() const { retur argument
98 isOther() const isOther() argument
102 isSymlink() const isSymlink() argument
104 isStatusKnown() const isStatusKnown() argument
106 exists() const exists() argument
124 makeAbsolute(SmallVectorImpl<char> &Path) const makeAbsolute() argument
136 getRealPath(const Twine &Path, SmallVectorImpl<char> &Output) const getRealPath() argument
268 adjustPath(const Twine &Path, SmallVectorImpl<char> &Storage) const adjustPath() argument
307 getCurrentWorkingDirectory() const getCurrentWorkingDirectory() argument
340 getRealPath(const Twine &Path, SmallVectorImpl<char> &Output) const getRealPath() argument
422 getCurrentWorkingDirectory() const getCurrentWorkingDirectory() argument
443 getRealPath(const Twine &Path, SmallVectorImpl<char> &Output) const getRealPath() argument
542 getFileName() const getFileName() argument
543 getKind() const getKind() argument
559 getStatus(const Twine &RequestedName) const getStatus() argument
562 getBuffer() const getBuffer() argument
581 getResolvedFile() const getResolvedFile() argument
633 getStatus(const Twine &RequestedName) const getStatus() argument
650 begin() const begin() argument
651 end() const end() argument
688 toString() const toString() argument
968 getRealPath(const Twine &Path, SmallVectorImpl<char> &Output) const getRealPath() argument
1047 getCurrentWorkingDirectory() const getCurrentWorkingDirectory() argument
1076 makeAbsolute(SmallVectorImpl<char> &Path) const makeAbsolute() argument
1119 getExternalContentsPrefixDir() const getExternalContentsPrefixDir() argument
1123 dump(raw_ostream &OS) const dump() argument
1128 dumpEntry(raw_ostream &OS, RedirectingFileSystem::Entry *E, int NumSpaces) const dumpEntry() argument
1148 dump() const dump() argument
1648 lookupPath(const Twine &Path_) const lookupPath() argument
1679 lookupPath(sys::path::const_iterator Start, sys::path::const_iterator End, RedirectingFileSystem::Entry *From) const lookupPath() argument
1816 getRealPath(const Twine &Path, SmallVectorImpl<char> &Output) const getRealPath() argument
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H A DYAMLParser.cpp1817 std::string Node::getVerbatimTag() const { in getVerbatimTag() argument
1878 void Node::setError(const Twine &Msg, Token &Tok) const { in setError() argument
1882 failed() const failed() argument
1886 getValue(SmallVectorImpl<char> &Storage) const getValue() argument
1919 unescapeDoubleQuoted( StringRef UnquotedValue , StringRef::size_type i , SmallVectorImpl<char> &Storage) const unescapeDoubleQuoted() argument
2312 setError(const Twine &Message, Token &Location) const setError() argument
2316 failed() const failed() argument
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/TableGen/
H A DTGParser.cpp58 LLVM_DUMP_METHOD void SubMultiClassReference::dump() const { in dump() argument
3444 dump() const dump() argument
3451 dump() const dump() argument
3461 dump() const dump() argument
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
H A DAArch64FrameLowering.cpp210 AArch64FrameLowering::getStackIDForScalableVectors() const { in getStackIDForScalableVectors() argument
220 bool AArch64FrameLowering::canUseRedZone(const MachineFunction &MF) const { in canUseRedZone() argument
238 bool AArch64FrameLowering::hasFP(const MachineFunctio argument
274 hasReservedCallFrame(const MachineFunction &MF) const hasReservedCallFrame() argument
278 eliminateCallFramePseudoInstr( MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const eliminateCallFramePseudoInstr() argument
416 canUseAsPrologue( const MachineBasicBlock &MBB) const canUseAsPrologue() argument
448 shouldCombineCSRLocalStackBump( MachineFunction &MF, uint64_t StackBumpBytes) const shouldCombineCSRLocalStackBump() argument
857 emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const emitPrologue() argument
1370 emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const emitEpilogue() argument
1661 getFrameIndexReference(const MachineFunction &MF, int FI, unsigned &FrameReg) const getFrameIndexReference() argument
1672 getNonLocalFrameIndexReference( const MachineFunction &MF, int FI) const getNonLocalFrameIndexReference() argument
1693 getSEHFrameIndexOffset(const MachineFunction &MF, int FI) const getSEHFrameIndexOffset() argument
1703 resolveFrameIndexReference( const MachineFunction &MF, int FI, unsigned &FrameReg, bool PreferFP, bool ForSimm) const resolveFrameIndexReference() argument
1714 resolveFrameOffsetReference( const MachineFunction &MF, int64_t ObjectOffset, bool isFixed, bool isSVE, unsigned &FrameReg, bool PreferFP, bool ForSimm) const resolveFrameOffsetReference() argument
2079 spillCalleeSavedRegisters( MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector<CalleeSavedInfo> &CSI, const TargetRegisterInfo *TRI) const spillCalleeSavedRegisters() argument
2221 restoreCalleeSavedRegisters( MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, std::vector<CalleeSavedInfo> &CSI, const TargetRegisterInfo *TRI) const restoreCalleeSavedRegisters() argument
2340 determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS) const determineCalleeSaves() argument
2496 enableStackSlotScavenging( const MachineFunction &MF) const enableStackSlotScavenging() argument
2595 estimateSVEStackObjectOffsets( MachineFrameInfo &MFI) const estimateSVEStackObjectOffsets() argument
2601 assignSVEStackObjectOffsets( MachineFrameInfo &MFI, int &MinCSFrameIndex, int &MaxCSFrameIndex) const assignSVEStackObjectOffsets() argument
2607 processFunctionBeforeFrameFinalized( MachineFunction &MF, RegScavenger *RS) const processFunctionBeforeFrameFinalized() argument
2655 getFrameIndexReferencePreferSP( const MachineFunction &MF, int FI, unsigned &FrameReg, bool IgnoreSPUpdates) const getFrameIndexReferencePreferSP() argument
2667 getWinEHParentFrameOffset( const MachineFunction &MF) const getWinEHParentFrameOffset() argument
2674 getWinEHFuncletFrameSize( const MachineFunction &MF) const getWinEHFuncletFrameSize() argument
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H A DAArch64Subtarget.h266 getTargetTriple() const getTargetTriple() argument
276 getProcFamily() const getProcFamily() argument
280 hasV8_1aOps() const hasV8_1aOps() argument
281 hasV8_2aOps() const hasV8_2aOps() argument
282 hasV8_3aOps() const hasV8_3aOps() argument
283 hasV8_4aOps() const hasV8_4aOps() argument
284 hasV8_5aOps() const hasV8_5aOps() argument
286 hasZeroCycleRegMove() const hasZeroCycleRegMove() argument
288 hasZeroCycleZeroingGP() const hasZeroCycleZeroingGP() argument
290 hasZeroCycleZeroingFP() const hasZeroCycleZeroingFP() argument
292 hasZeroCycleZeroingFPWorkaround() const hasZeroCycleZeroingFPWorkaround() argument
296 requiresStrictAlign() const requiresStrictAlign() argument
300 getMinVectorRegisterBitWidth() const getMinVectorRegisterBitWidth() argument
304 isXRegisterReserved(size_t i) const isXRegisterReserved() argument
305 getNumXRegisterReserved() const getNumXRegisterReserved() argument
306 isXRegCustomCalleeSaved(size_t i) const isXRegCustomCalleeSaved() argument
309 hasCustomCallingConv() const hasCustomCallingConv() argument
310 hasFPARMv8() const hasFPARMv8() argument
311 hasNEON() const hasNEON() argument
312 hasCrypto() const hasCrypto() argument
313 hasDotProd() const hasDotProd() argument
314 hasCRC() const hasCRC() argument
315 hasLSE() const hasLSE() argument
316 hasRAS() const hasRAS() argument
317 hasRDM() const hasRDM() argument
318 hasSM4() const hasSM4() argument
319 hasSHA3() const hasSHA3() argument
320 hasSHA2() const hasSHA2() argument
321 hasAES() const hasAES() argument
322 balanceFPOps() const balanceFPOps() argument
323 predictableSelectIsExpensive() const predictableSelectIsExpensive() argument
326 hasCustomCheapAsMoveHandling() const hasCustomCheapAsMoveHandling() argument
327 hasExynosCheapAsMoveHandling() const hasExynosCheapAsMoveHandling() argument
328 isMisaligned128StoreSlow() const isMisaligned128StoreSlow() argument
329 isPaired128Slow() const isPaired128Slow() argument
330 isSTRQroSlow() const isSTRQroSlow() argument
331 useAlternateSExtLoadCVTF32Pattern() const useAlternateSExtLoadCVTF32Pattern() argument
334 hasArithmeticBccFusion() const hasArithmeticBccFusion() argument
335 hasArithmeticCbzFusion() const hasArithmeticCbzFusion() argument
336 hasFuseAddress() const hasFuseAddress() argument
337 hasFuseAES() const hasFuseAES() argument
338 hasFuseArithmeticLogic() const hasFuseArithmeticLogic() argument
339 hasFuseCCSelect() const hasFuseCCSelect() argument
340 hasFuseCryptoEOR() const hasFuseCryptoEOR() argument
341 hasFuseLiterals() const hasFuseLiterals() argument
344 hasFusion() const hasFusion() argument
350 useEL1ForTP() const useEL1ForTP() argument
351 useEL2ForTP() const useEL2ForTP() argument
352 useEL3ForTP() const useEL3ForTP() argument
354 useRSqrt() const useRSqrt() argument
355 force32BitJumpTables() const force32BitJumpTables() argument
356 getMaxInterleaveFactor() const getMaxInterleaveFactor() argument
357 getVectorInsertExtractBaseCost() const getVectorInsertExtractBaseCost() argument
366 getPrefFunctionLogAlignment() const getPrefFunctionLogAlignment() argument
369 getPrefLoopLogAlignment() const getPrefLoopLogAlignment() argument
371 getMaximumJumpTableSize() const getMaximumJumpTableSize() argument
373 getWideningBaseCost() const getWideningBaseCost() argument
379 hasPerfMon() const hasPerfMon() argument
380 hasFullFP16() const hasFullFP16() argument
381 hasFP16FML() const hasFP16FML() argument
382 hasSPE() const hasSPE() argument
383 hasLSLFast() const hasLSLFast() argument
384 hasSVE() const hasSVE() argument
385 hasSVE2() const hasSVE2() argument
386 hasRCPC() const hasRCPC() argument
387 hasAggressiveFMA() const hasAggressiveFMA() argument
388 hasAlternativeNZCV() const hasAlternativeNZCV() argument
389 hasFRInt3264() const hasFRInt3264() argument
390 hasSpecRestrict() const hasSpecRestrict() argument
391 hasSSBS() const hasSSBS() argument
392 hasSB() const hasSB() argument
393 hasPredRes() const hasPredRes() argument
394 hasCCDP() const hasCCDP() argument
395 hasBTI() const hasBTI() argument
396 hasRandGen() const hasRandGen() argument
397 hasMTE() const hasMTE() argument
398 hasTME() const hasTME() argument
400 hasSVE2AES() const hasSVE2AES() argument
401 hasSVE2SM4() const hasSVE2SM4() argument
402 hasSVE2SHA3() const hasSVE2SHA3() argument
403 hasSVE2BitPerm() const hasSVE2BitPerm() argument
405 isLittleEndian() const isLittleEndian() argument
407 isTargetDarwin() const isTargetDarwin() argument
408 isTargetIOS() const isTargetIOS() argument
409 isTargetLinux() const isTargetLinux() argument
410 isTargetWindows() const isTargetWindows() argument
411 isTargetAndroid() const isTargetAndroid() argument
412 isTargetFuchsia() const isTargetFuchsia() argument
414 isTargetCOFF() const isTargetCOFF() argument
415 isTargetELF() const isTargetELF() argument
416 isTargetMachO() const isTargetMachO() argument
418 isTargetILP32() const isTargetILP32() argument
422 hasVH() const hasVH() argument
423 hasPAN() const hasPAN() argument
424 hasLOR() const hasLOR() argument
426 hasPsUAO() const hasPsUAO() argument
427 hasPAN_RWV() const hasPAN_RWV() argument
428 hasCCPP() const hasCCPP() argument
430 hasPA() const hasPA() argument
431 hasJS() const hasJS() argument
432 hasCCIDX() const hasCCIDX() argument
433 hasComplxNum() const hasComplxNum() argument
435 hasNV() const hasNV() argument
436 hasRASv8_4() const hasRASv8_4() argument
437 hasMPAM() const hasMPAM() argument
438 hasDIT() const hasDIT() argument
439 hasTRACEV8_4() const hasTRACEV8_4() argument
440 hasAM() const hasAM() argument
441 hasSEL2() const hasSEL2() argument
442 hasPMU() const hasPMU() argument
443 hasTLB_RMI() const hasTLB_RMI() argument
444 hasFMI() const hasFMI() argument
445 hasRCPC_IMMO() const hasRCPC_IMMO() argument
453 useSmallAddressing() const useSmallAddressing() argument
486 isCallingConvWin64(CallingConv::ID CC) const isCallingConvWin64() argument
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
H A DAMDGPUCodeGenPrepare.cpp204 getBaseElementBitWidth(const Type *T) const getBaseElementBitWidth() argument
212 getI32Ty(IRBuilder< &B, const Type *T) const getI32Ty() argument
220 isSigned(const BinaryOperator &I) const isSigned() argument
225 isSigned(const SelectInst &I) const isSigned() argument
230 needsPromotionToI32(const Type *T) const needsPromotionToI32() argument
275 canWidenScalarExtLoad(LoadInst &I) const canWidenScalarExtLoad() argument
285 promoteUniformOpToI32(BinaryOperator &I) const promoteUniformOpToI32() argument
332 promoteUniformOpToI32(ICmpInst &I) const promoteUniformOpToI32() argument
359 promoteUniformOpToI32(SelectInst &I) const promoteUniformOpToI32() argument
388 promoteUniformBitreverseToI32( IntrinsicInst &I) const promoteUniformBitreverseToI32() argument
414 numBitsUnsigned(Value *Op, unsigned ScalarSize) const numBitsUnsigned() argument
420 numBitsSigned(Value *Op, unsigned ScalarSize) const numBitsSigned() argument
427 isI24(Value *V, unsigned ScalarSize) const isI24() argument
433 isU24(Value *V, unsigned ScalarSize) const isU24() argument
462 replaceMulWithMul24(BinaryOperator &I) const replaceMulWithMul24() argument
636 expandDivRem24(IRBuilder< &Builder, BinaryOperator &I, Value *Num, Value *Den, bool IsDiv, bool IsSigned) const expandDivRem24() argument
740 expandDivRem32(IRBuilder< &Builder, BinaryOperator &I, Value *Num, Value *Den) const expandDivRem32() argument
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H A DAMDGPULibCalls.cpp492 isUnsafeMath(const CallInst *CI) const isUnsafeMath() argument
501 useNativeFunc(const StringRef F) const useNativeFunc() argument
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H A DAMDILCFGStructurizer.cpp182 void printOrderedBlocks() const { in printOrderedBlocks() argument
345 getSCCNum(MachineBasicBlock *MBB) const getSCCNum() argument
352 getLoopLandInfo(MachineLoop *LoopRep) const getLoopLandInfo() argument
360 hasBackEdge(MachineBasicBlock *MBB) const hasBackEdge() argument
368 isRetiredBlock(MachineBasicBlock *MBB) const isRetiredBlock() argument
375 isActiveLoophead(MachineBasicBlock *MBB) const isActiveLoophead() argument
388 singlePathTo( MachineBasicBlock *SrcMBB, MachineBasicBlock *DstMBB, bool AllowSideEntry) const singlePathTo() argument
406 countActiveBlock(MBBVector::const_iterator It, MBBVector::const_iterator E) const countActiveBlock() argument
417 needMigrateBlock(MachineBasicBlock *MBB) const needMigrateBlock() argument
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H A DR600ISelLowering.cpp475 SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { in LowerOperation() argument
292 EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *BB) const EmitInstrWithCustomInserter() argument
652 ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results, SelectionDAG &DAG) const ReplaceNodeResults() argument
694 vectorToVerticalVector(SelectionDAG &DAG, SDValue Vector) const vectorToVerticalVector() argument
710 LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const LowerEXTRACT_VECTOR_ELT() argument
725 LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const LowerINSERT_VECTOR_ELT() argument
742 LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op, SelectionDAG &DAG) const LowerGlobalAddress() argument
757 LowerTrig(SDValue Op, SelectionDAG &DAG) const LowerTrig() argument
791 LowerSHLParts(SDValue Op, SelectionDAG &DAG) const LowerSHLParts() argument
827 LowerSRXParts(SDValue Op, SelectionDAG &DAG) const LowerSRXParts() argument
865 LowerUADDSUBO(SDValue Op, SelectionDAG &DAG, unsigned mainop, unsigned ovf) const LowerUADDSUBO() argument
883 lowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const lowerFP_TO_UINT() argument
893 lowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const lowerFP_TO_SINT() argument
903 LowerImplicitParameter(SelectionDAG &DAG, EVT VT, const SDLoc &DL, unsigned DwordOffset) const LowerImplicitParameter() argument
918 isZero(SDValue Op) const isZero() argument
928 isHWTrueValue(SDValue Op) const isHWTrueValue() argument
935 isHWFalseValue(SDValue Op) const isHWFalseValue() argument
942 LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const LowerSELECT_CC() argument
1088 stackPtrToRegIndex(SDValue Ptr, unsigned StackWidth, SelectionDAG &DAG) const stackPtrToRegIndex() argument
1110 getStackAddress(unsigned StackWidth, unsigned ElemIdx, unsigned &Channel, unsigned &PtrIncr) const getStackAddress() argument
1139 lowerPrivateTruncStore(StoreSDNode *Store, SelectionDAG &DAG) const lowerPrivateTruncStore() argument
1229 LowerSTORE(SDValue Op, SelectionDAG &DAG) const LowerSTORE() argument
1384 lowerPrivateExtLoad(SDValue Op, SelectionDAG &DAG) const lowerPrivateExtLoad() argument
1440 LowerLOAD(SDValue Op, SelectionDAG &DAG) const LowerLOAD() argument
1529 LowerBRCOND(SDValue Op, SelectionDAG &DAG) const LowerBRCOND() argument
1538 lowerFrameIndex(SDValue Op, SelectionDAG &DAG) const lowerFrameIndex() argument
1553 CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg) const CCAssignFnForCall() argument
1578 LowerFormalArguments( SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const LowerFormalArguments() argument
1648 getSetCCResultType(const DataLayout &DL, LLVMContext &, EVT VT) const getSetCCResultType() argument
1655 canMergeStoresTo(unsigned AS, EVT MemVT, const SelectionDAG &DAG) const canMergeStoresTo() argument
1664 allowsMisalignedMemoryAccesses( EVT VT, unsigned AddrSpace, unsigned Align, MachineMemOperand::Flags Flags, bool *IsFast) const allowsMisalignedMemoryAccesses() argument
1768 OptimizeSwizzle(SDValue BuildVector, SDValue Swz[4], SelectionDAG &DAG, const SDLoc &DL) const OptimizeSwizzle() argument
1792 constBufferLoad(LoadSDNode *LoadNode, int Block, SelectionDAG &DAG) const constBufferLoad() argument
1842 PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const PerformDAGCombine() argument
2069 FoldOperand(SDNode *ParentNode, unsigned SrcIdx, SDValue &Src, SDValue &Neg, SDValue &Abs, SDValue &Sel, SDValue &Imm, SelectionDAG &DAG) const FoldOperand() argument
2201 PostISelFolding(MachineSDNode *Node, SelectionDAG &DAG) const PostISelFolding() argument
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H A DSIFoldOperands.cpp563 foldOperand( MachineOperand &OpToFold, MachineInstr *UseMI, int UseOpIdx, SmallVectorImpl<FoldCandidate> &FoldList, SmallVectorImpl<MachineInstr *> &CopiesToReplace) const foldOperand() argument
1135 foldInstOperand(MachineInstr &MI, MachineOperand &OpToFold) const foldInstOperand() argument
1263 isClamp(const MachineInstr &MI) const isClamp() argument
1378 isOMod(const MachineInstr &MI) const isOMod() argument
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H A DSIInsertWaitcnts.cpp94 bool operator==(const enum_iterator &RHS) const { return Value == RHS.Value; } in operator ==() argument
96 EnumT operator*() const { return Value; } in operator *() argument
219 uint32_t getScoreLB(InstCounterType T) const { in getScoreLB() argument
226 uint32_t getScoreUB(InstCounterType T) const { in getScoreUB() argument
270 getMaxVGPR() const getMaxVGPR() argument
271 getMaxSGPR() const getMaxSGPR() argument
284 hasPending() const hasPending() argument
285 hasPendingEvent(WaitEventType E) const hasPendingEvent() argument
289 hasPendingFlat() const hasPendingFlat() argument
417 isForceEmitWaitcnt() const isForceEmitWaitcnt() argument
463 getRegInterval(const MachineInstr *MI, const SIInstrInfo *TII, const MachineRegisterInfo *MRI, const SIRegisterInfo *TRI, unsigned OpNo, bool Def) const getRegInterval() argument
721 simplifyWaitcnt(AMDGPU::Waitcnt &Wait) const simplifyWaitcnt() argument
728 simplifyWaitcnt(InstCounterType T, unsigned &Count) const simplifyWaitcnt() argument
739 determineWait(InstCounterType T, uint32_t ScoreToWait, AMDGPU::Waitcnt &Wait) const determineWait() argument
791 counterOutOfOrder(InstCounterType T) const counterOutOfOrder() argument
1199 mayAccessLDSThroughFlat(const MachineInstr &MI) const mayAccessLDSThroughFlat() argument
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H A DSILoadStoreOptimizer.cpp938 read2Opcode(unsigned EltSize) const read2Opcode() argument
944 read2ST64Opcode(unsigned EltSize) const read2ST64Opcode() argument
1035 write2Opcode(unsigned EltSize) const write2Opcode() argument
1042 write2ST64Opcode(unsigned EltSize) const write2ST64Opcode() argument
1572 createRegOrImm(int32_t Val, MachineInstr &MI) const createRegOrImm() argument
1588 computeBase(MachineInstr &MI, const MemAddress &Addr) const computeBase() argument
1646 updateBaseAndOffset(MachineInstr &MI, unsigned NewBase, int32_t NewOffset) const updateBaseAndOffset() argument
1656 extractConstOffset(const MachineOperand &Op) const extractConstOffset() argument
1681 processBaseWithConstOffset(const MachineOperand &Base, MemAddress &Addr) const processBaseWithConstOffset() argument
1734 promoteConstantOffsetToImm( MachineInstr &MI, MemInfoMap &Visited, SmallPtrSet<MachineInstr *, 4> &AnchorList) const promoteConstantOffsetToImm() argument
1883 addInstToMergeableList(const CombineInfo &CI, std::list<std::list<CombineInfo> > &MergeableInsts) const addInstToMergeableList() argument
1897 collectMergeableInsts(MachineBasicBlock &MBB, std::list<std::list<CombineInfo> > &MergeableInsts) const collectMergeableInsts() argument
[all...]
H A DSIMachineFunctionInfo.h491 getSGPRToVGPRSpills(int FrameIndex) const getSGPRToVGPRSpills() argument
497 getSGPRSpillVGPRs() const getSGPRSpillVGPRs() argument
501 getAGPRSpillVGPRs() const getAGPRSpillVGPRs() argument
505 getVGPRSpillAGPRs() const getVGPRSpillAGPRs() argument
509 getVGPRToAGPRSpill(int FrameIndex, unsigned Lane) const getVGPRToAGPRSpill() argument
521 hasCalculatedTID() const hasCalculatedTID() argument
522 getTIDReg() const getTIDReg() argument
525 getBytesInStackArgArea() const getBytesInStackArgArea() argument
591 hasPrivateSegmentBuffer() const hasPrivateSegmentBuffer() argument
595 hasDispatchPtr() const hasDispatchPtr() argument
599 hasQueuePtr() const hasQueuePtr() argument
603 hasKernargSegmentPtr() const hasKernargSegmentPtr() argument
607 hasDispatchID() const hasDispatchID() argument
611 hasFlatScratchInit() const hasFlatScratchInit() argument
615 hasWorkGroupIDX() const hasWorkGroupIDX() argument
619 hasWorkGroupIDY() const hasWorkGroupIDY() argument
623 hasWorkGroupIDZ() const hasWorkGroupIDZ() argument
627 hasWorkGroupInfo() const hasWorkGroupInfo() argument
631 hasPrivateSegmentWaveByteOffset() const hasPrivateSegmentWaveByteOffset() argument
635 hasWorkItemIDX() const hasWorkItemIDX() argument
639 hasWorkItemIDY() const hasWorkItemIDY() argument
643 hasWorkItemIDZ() const hasWorkItemIDZ() argument
647 hasImplicitArgPtr() const hasImplicitArgPtr() argument
651 hasImplicitBufferPtr() const hasImplicitBufferPtr() argument
659 getArgInfo() const getArgInfo() argument
664 getPreloadedValue(AMDGPUFunctionArgInfo::PreloadedValue Value) const getPreloadedValue() argument
668 getPreloadedReg(AMDGPUFunctionArgInfo::PreloadedValue Value) const getPreloadedReg() argument
673 getGITPtrHigh() const getGITPtrHigh() argument
677 get32BitAddressHighBits() const get32BitAddressHighBits() argument
681 getGDSSize() const getGDSSize() argument
685 getNumUserSGPRs() const getNumUserSGPRs() argument
689 getNumPreloadedSGPRs() const getNumPreloadedSGPRs() argument
693 getPrivateSegmentWaveByteOffsetSystemSGPR() const getPrivateSegmentWaveByteOffsetSystemSGPR() argument
699 getScratchRSrcReg() const getScratchRSrcReg() argument
708 getScratchWaveOffsetReg() const getScratchWaveOffsetReg() argument
712 getFrameOffsetReg() const getFrameOffsetReg() argument
730 getStackPtrOffsetReg() const getStackPtrOffsetReg() argument
739 getQueuePtrUserSGPR() const getQueuePtrUserSGPR() argument
743 getImplicitBufferPtrUserSGPR() const getImplicitBufferPtrUserSGPR() argument
747 hasSpilledSGPRs() const hasSpilledSGPRs() argument
755 hasSpilledVGPRs() const hasSpilledVGPRs() argument
763 hasNonSpillStackObjects() const hasNonSpillStackObjects() argument
771 isStackRealigned() const isStackRealigned() argument
779 getNumSpilledSGPRs() const getNumSpilledSGPRs() argument
783 getNumSpilledVGPRs() const getNumSpilledVGPRs() argument
795 getPSInputAddr() const getPSInputAddr() argument
799 getPSInputEnable() const getPSInputEnable() argument
803 isPSInputAllocated(unsigned Index) const isPSInputAllocated() argument
815 returnsVoid() const returnsVoid() argument
825 getFlatWorkGroupSizes() const getFlatWorkGroupSizes() argument
830 getMinFlatWorkGroupSize() const getMinFlatWorkGroupSize() argument
835 getMaxFlatWorkGroupSize() const getMaxFlatWorkGroupSize() argument
841 getWavesPerEU() const getWavesPerEU() argument
846 getMinWavesPerEU() const getMinWavesPerEU() argument
851 getMaxWavesPerEU() const getMaxWavesPerEU() argument
856 getWorkGroupIDSGPR(unsigned Dim) const getWorkGroupIDSGPR() argument
871 getLDSWaveSpillSize() const getLDSWaveSpillSize() argument
902 getOccupancy() const getOccupancy() argument
906 getMinAllowedOccupancy() const getMinAllowedOccupancy() argument
[all...]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
H A DARMConstantIslandPass.cpp971 getUserOffset(CPUser &U) const getUserOffset() argument
[all...]
H A DARMFrameLowering.cpp82 bool ARMFrameLowering::keepFramePointer(const MachineFunction &MF) const { in keepFramePointer() argument
91 bool ARMFrameLowering::enableCalleeSaveSkip(const MachineFunction &MF) const { in enableCalleeSaveSkip() argument
104 bool ARMFrameLowering::hasFP(const MachineFunction &MF) const { in hasFP() argument
123 bool ARMFrameLowering::hasReservedCallFrame(const MachineFunctio argument
141 canSimplifyCallFramePseudos(const MachineFunction &MF) const canSimplifyCallFramePseudos() argument
356 emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const emitPrologue() argument
770 emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const emitEpilogue() argument
882 getFrameIndexReference(const MachineFunction &MF, int FI, unsigned &FrameReg) const getFrameIndexReference() argument
888 ResolveFrameIndexReference(const MachineFunction &MF, int FI, unsigned &FrameReg, int SPAdj) const ResolveFrameIndexReference() argument
970 emitPushInst(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector<CalleeSavedInfo> &CSI, unsigned StmOpc, unsigned StrOpc, bool NoGap, bool(*Func)(unsigned, bool), unsigned NumAlignedDPRCS2Regs, unsigned MIFlags) const emitPushInst() argument
1048 emitPopInst(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, std::vector<CalleeSavedInfo> &CSI, unsigned LdmOpc, unsigned LdrOpc, bool isVarArg, bool NoGap, bool(*Func)(unsigned, bool), unsigned NumAlignedDPRCS2Regs) const emitPopInst() argument
1425 spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector<CalleeSavedInfo> &CSI, const TargetRegisterInfo *TRI) const spillCalleeSavedRegisters() argument
1456 restoreCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, std::vector<CalleeSavedInfo> &CSI, const TargetRegisterInfo *TRI) const restoreCalleeSavedRegisters() argument
1633 determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS) const determineCalleeSaves() argument
2133 getCalleeSaves(const MachineFunction &MF, BitVector &SavedRegs) const getCalleeSaves() argument
2145 eliminateCallFramePseudoInstr( MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const eliminateCallFramePseudoInstr() argument
2245 adjustForSegmentedStacks( MachineFunction &MF, MachineBasicBlock &PrologueMBB) const adjustForSegmentedStacks() argument
[all...]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp243 const char *AVRTargetLowering::getTargetNodeName(unsigned Opcode) const { in getTargetNodeName() argument
272 EVT AVRTargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &, in getSetCCResultType() argument
278 SDValue AVRTargetLowering::LowerShifts(SDValue Op, SelectionDAG &DAG) const { in LowerShifts() argument
339 SDValue AVRTargetLowering::LowerDivRem(SDValue Op, SelectionDAG &DAG) const { in LowerDivRem() argument
398 LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const LowerGlobalAddress() argument
411 LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const LowerBlockAddress() argument
443 getAVRCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC, SDValue &AVRcc, SelectionDAG &DAG, SDLoc DL) const getAVRCmp() argument
619 LowerBR_CC(SDValue Op, SelectionDAG &DAG) const LowerBR_CC() argument
634 LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const LowerSELECT_CC() argument
651 LowerSETCC(SDValue Op, SelectionDAG &DAG) const LowerSETCC() argument
668 LowerVASTART(SDValue Op, SelectionDAG &DAG) const LowerVASTART() argument
683 LowerOperation(SDValue Op, SelectionDAG &DAG) const LowerOperation() argument
715 ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results, SelectionDAG &DAG) const ReplaceNodeResults() argument
744 isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I) const isLegalAddressingMode() argument
772 getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const getPreIndexedAddressParts() argument
828 getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const getPostIndexedAddressParts() argument
875 isOffsetFoldingLegal( const GlobalAddressSDNode *GA) const isOffsetFoldingLegal() argument
1049 LowerFormalArguments( SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const LowerFormalArguments() argument
1145 LowerCall(TargetLowering::CallLoweringInfo &CLI, SmallVectorImpl<SDValue> &InVals) const LowerCall() argument
1311 LowerCallResult( SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const LowerCallResult() argument
1347 CCAssignFnForReturn(CallingConv::ID CC) const CCAssignFnForReturn() argument
1357 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const CanLowerReturn() argument
1370 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SDLoc &dl, SelectionDAG &DAG) const LowerReturn() argument
1436 insertShift(MachineInstr &MI, MachineBasicBlock *BB) const insertShift() argument
1580 insertMul(MachineInstr &MI, MachineBasicBlock *BB) const insertMul() argument
1596 EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const EmitInstrWithCustomInserter() argument
1687 getConstraintType(StringRef Constraint) const getConstraintType() argument
1727 getInlineAsmMemConstraint(StringRef ConstraintCode) const getInlineAsmMemConstraint() argument
1738 getSingleConstraintMatchWeight( AsmOperandInfo &info, const char *constraint) const getSingleConstraintMatchWeight() argument
1851 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const getRegForInlineAsmConstraint() argument
1901 LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector<SDValue> &Ops, SelectionDAG &DAG) const LowerAsmOperandForConstraint() argument
2008 getRegisterByName(const char *RegName, LLT VT, const MachineFunction &MF) const getRegisterByName() argument
[all...]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
H A DHexagonConstExtenders.cpp580 dump() const dump() argument
586 dump(const Node *N) const dump() argument
602 order(Node *N, SmallVectorImpl<Node*> &Seq) const order() argument
610 nodesWith(Node *N, int32_t P, bool CheckA, SmallVectorImpl<Node*> &Seq) const nodesWith() argument
718 operator <(const HCE::ExtRoot &ER) const operator <() argument
765 operator <(const HCE::ExtValue &EV) const operator <() argument
772 operator MachineOperand() const operator MachineOperand() argument
798 isStoreImmediate(unsigned Opc) const isStoreImmediate() argument
816 isRegOffOpcode(unsigned Opc) const isRegOffOpcode() argument
865 getRegOffOpcode(unsigned ExtOpc) const getRegOffOpcode() argument
965 getDirectRegReplacement(unsigned ExtOpc) const getDirectRegReplacement() argument
1048 getOffsetRange(Register Rb, const MachineInstr &MI) const getOffsetRange() argument
1099 getOffsetRange(const ExtDesc &ED) const getOffsetRange() argument
1128 getOffsetRange(Register Rd) const getOffsetRange() argument
1915 getOperandIndex(const MachineInstr &MI, const MachineOperand &Op) const getOperandIndex() argument
1923 getPredicateOp(const MachineInstr &MI) const getPredicateOp() argument
1935 getLoadResultOp(const MachineInstr &MI) const getLoadResultOp() argument
1940 getStoredValueOp(const MachineInstr &MI) const getStoredValueOp() argument
[all...]
H A DHexagonHardwareLoops.cpp341 isReg() const isReg() argument
342 isImm() const isImm() argument
344 getReg() const getReg() argument
349 getSubReg() const getSubReg() argument
354 getImm() const getImm() argument
359 print(raw_ostream &OS, const TargetRegisterInfo *TRI = nullptr) const print() argument
402 findInductionRegister(MachineLoop *L, unsigned &Reg, int64_t &IVBump, MachineInstr *&IVOp ) const findInductionRegister() argument
508 getComparisonKind(unsigned CondOpc, MachineOperand *InitialValue, const MachineOperand *EndValue, int64_t IVBump) const getComparisonKind() argument
725 computeCount(MachineLoop *Loop, const MachineOperand *Start, const MachineOperand *End, unsigned IVReg, int64_t IVBump, Comparison::Kind Cmp) const computeCount() argument
989 isInvalidLoopOperation(const MachineInstr *MI, bool IsInnerHWLoop) const isInvalidLoopOperation() argument
1012 containsInvalidInstruction(MachineLoop *L, bool IsInnerHWLoop) const containsInvalidInstruction() argument
1034 isDead(const MachineInstr *MI, SmallVectorImpl<MachineInstr *> &DeadPhis) const isDead() argument
1365 isLoopFeeder(MachineLoop *L, MachineBasicBlock *A, MachineInstr *MI, const MachineOperand *MO, LoopFeederMap &LoopFeederPhi) const isLoopFeeder() argument
1387 phiMayWrapOrUnderflow( MachineInstr *Phi, const MachineOperand *EndVal, MachineBasicBlock *MBB, MachineLoop *L, LoopFeederMap &LoopFeederPhi) const phiMayWrapOrUnderflow() argument
1415 loopCountMayWrapOrUnderFlow( const MachineOperand *InitVal, const MachineOperand *EndVal, MachineBasicBlock *MBB, MachineLoop *L, LoopFeederMap &LoopFeederPhi) const loopCountMayWrapOrUnderFlow() argument
1498 checkForImmediate(const MachineOperand &MO, int64_t &Val) const checkForImmediate() argument
[all...]
H A DHexagonISelLoweringHVX.cpp218 HexagonTargetLowering::typeJoin(const TypePair &Tys) const { in typeJoin() argument
227 HexagonTargetLowering::typeSplit(MVT VecTy) const { in typeSplit() argument
208 getInt(unsigned IntId, MVT ResTy, ArrayRef<SDValue> Ops, const SDLoc &dl, SelectionDAG &DAG) const getInt() argument
236 typeExtElem(MVT VecTy, unsigned Factor) const typeExtElem() argument
243 typeTruncElem(MVT VecTy, unsigned Factor) const typeTruncElem() argument
250 opCastElem(SDValue Vec, MVT ElemTy, SelectionDAG &DAG) const opCastElem() argument
259 opJoin(const VectorPair &Ops, const SDLoc &dl, SelectionDAG &DAG) const opJoin() argument
266 opSplit(SDValue Vec, const SDLoc &dl, SelectionDAG &DAG) const opSplit() argument
275 isHvxSingleTy(MVT Ty) const isHvxSingleTy() argument
281 isHvxPairTy(MVT Ty) const isHvxPairTy() argument
287 convertToByteIndex(SDValue ElemIdx, MVT ElemTy, SelectionDAG &DAG) const convertToByteIndex() argument
303 getIndexInWord32(SDValue Idx, MVT ElemTy, SelectionDAG &DAG) const getIndexInWord32() argument
319 getByteShuffle(const SDLoc &dl, SDValue Op0, SDValue Op1, ArrayRef<int> Mask, SelectionDAG &DAG) const getByteShuffle() argument
350 buildHvxVectorReg(ArrayRef<SDValue> Values, const SDLoc &dl, MVT VecTy, SelectionDAG &DAG) const buildHvxVectorReg() argument
502 createHvxPrefixPred(SDValue PredV, const SDLoc &dl, unsigned BitBytes, bool ZeroFill, SelectionDAG &DAG) const createHvxPrefixPred() argument
591 buildHvxVectorPred(ArrayRef<SDValue> Values, const SDLoc &dl, MVT VecTy, SelectionDAG &DAG) const buildHvxVectorPred() argument
664 extractHvxElementReg(SDValue VecV, SDValue IdxV, const SDLoc &dl, MVT ResTy, SelectionDAG &DAG) const extractHvxElementReg() argument
688 extractHvxElementPred(SDValue VecV, SDValue IdxV, const SDLoc &dl, MVT ResTy, SelectionDAG &DAG) const extractHvxElementPred() argument
707 insertHvxElementReg(SDValue VecV, SDValue IdxV, SDValue ValV, const SDLoc &dl, SelectionDAG &DAG) const insertHvxElementReg() argument
752 insertHvxElementPred(SDValue VecV, SDValue IdxV, SDValue ValV, const SDLoc &dl, SelectionDAG &DAG) const insertHvxElementPred() argument
768 extractHvxSubvectorReg(SDValue VecV, SDValue IdxV, const SDLoc &dl, MVT ResTy, SelectionDAG &DAG) const extractHvxSubvectorReg() argument
813 extractHvxSubvectorPred(SDValue VecV, SDValue IdxV, const SDLoc &dl, MVT ResTy, SelectionDAG &DAG) const extractHvxSubvectorPred() argument
877 insertHvxSubvectorReg(SDValue VecV, SDValue SubV, SDValue IdxV, const SDLoc &dl, SelectionDAG &DAG) const insertHvxSubvectorReg() argument
964 insertHvxSubvectorPred(SDValue VecV, SDValue SubV, SDValue IdxV, const SDLoc &dl, SelectionDAG &DAG) const insertHvxSubvectorPred() argument
1009 extendHvxVectorPred(SDValue VecV, const SDLoc &dl, MVT ResTy, bool ZeroExt, SelectionDAG &DAG) const extendHvxVectorPred() argument
1026 LowerHvxBuildVector(SDValue Op, SelectionDAG &DAG) const LowerHvxBuildVector() argument
1051 LowerHvxConcatVectors(SDValue Op, SelectionDAG &DAG) const LowerHvxConcatVectors() argument
1141 LowerHvxExtractElement(SDValue Op, SelectionDAG &DAG) const LowerHvxExtractElement() argument
1155 LowerHvxInsertElement(SDValue Op, SelectionDAG &DAG) const LowerHvxInsertElement() argument
1169 LowerHvxExtractSubvector(SDValue Op, SelectionDAG &DAG) const LowerHvxExtractSubvector() argument
1188 LowerHvxInsertSubvector(SDValue Op, SelectionDAG &DAG) const LowerHvxInsertSubvector() argument
1205 LowerHvxAnyExt(SDValue Op, SelectionDAG &DAG) const LowerHvxAnyExt() argument
1219 LowerHvxSignExt(SDValue Op, SelectionDAG &DAG) const LowerHvxSignExt() argument
1229 LowerHvxZeroExt(SDValue Op, SelectionDAG &DAG) const LowerHvxZeroExt() argument
1239 LowerHvxCttz(SDValue Op, SelectionDAG &DAG) const LowerHvxCttz() argument
1274 LowerHvxMul(SDValue Op, SelectionDAG &DAG) const LowerHvxMul() argument
1328 LowerHvxMulh(SDValue Op, SelectionDAG &DAG) const LowerHvxMulh() argument
1434 LowerHvxExtend(SDValue Op, SelectionDAG &DAG) const LowerHvxExtend() argument
1442 LowerHvxShift(SDValue Op, SelectionDAG &DAG) const LowerHvxShift() argument
1449 SplitHvxPairOp(SDValue Op, SelectionDAG &DAG) const SplitHvxPairOp() argument
1482 SplitHvxMemOp(SDValue Op, SelectionDAG &DAG) const SplitHvxMemOp() argument
1525 LowerHvxOperation(SDValue Op, SelectionDAG &DAG) const LowerHvxOperation() argument
1593 PerformHvxDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const PerformHvxDAGCombine() argument
1615 isHvxOperation(SDValue Op) const isHvxOperation() argument
[all...]
H A DHexagonLoopIdiomRecognition.cpp286 print(raw_ostream &OS, const Value *V) const print() argument
454 equal(const Instruction *I, const Instruction *J) const equal() argument
478 find(Value *Tree, Value *Sub) const find() argument
570 getPmpyType() const getPmpyType() argument
2303 coverLoop(Loop *L, SmallVectorImpl<Instruction*> &Insts) const coverLoop() argument
[all...]
H A DRDFGraph.cpp377 id(const NodeBase *P) const id() argument
408 getRegRef(const DataFlowGraph &G) const getRegRef() argument
460 getFirstMember(const DataFlowGraph &G) const getFirstMember() argument
467 getLastMember(const DataFlowGraph &G) const getLastMember() argument
527 members(const DataFlowGraph &G) const members() argument
576 findBlock(const MachineBasicBlock *BB, const DataFlowGraph &G) const findBlock() argument
598 isPreserving(const MachineInstr &In, unsigned OpNum) const isPreserving() argument
604 isClobbering(const MachineInstr &In, unsigned OpNum) const isClobbering() argument
617 isFixedReg(const MachineInstr &In, unsigned OpNum) const isFixedReg() argument
678 size() const size() argument
717 nextUp(unsigned P) const nextUp() argument
964 makeRegRef(unsigned Reg, unsigned Sub) const makeRegRef() argument
973 makeRegRef(const MachineOperand &Op) const makeRegRef() argument
980 restrictRef(RegisterRef AR, RegisterRef BR) const restrictRef() argument
1128 getRelatedRefs(NodeAddr<InstrNode*> IA, NodeAddr<RefNode*> RA) const getRelatedRefs() argument
1154 getNextRelated(NodeAddr<InstrNode*> IA, NodeAddr<RefNode*> RA) const getNextRelated() argument
1193 locateNextRef(NodeAddr<InstrNode*> IA, NodeAddr<RefNode*> RA, Predicate P) const locateNextRef() argument
1236 getNextShadow(NodeAddr<InstrNode*> IA, NodeAddr<RefNode*> RA) const getNextShadow() argument
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