| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| H A D | Thumb2InstrInfo.cpp | 45 void Thumb2InstrInfo::getNoop(MCInst &NopInst) const { in getNoop() argument
52 unsigned Thumb2InstrInfo::getUnindexedOpcode(unsigned Opc) const { in getUnindexedOpcode() argument
58 ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail, MachineBasicBlock *NewDest) const ReplaceTailWithBranchTo() argument
109 isLegalToSplitMBBAt(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const isLegalToSplitMBBAt() argument
121 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const copyPhysReg() argument
135 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const storeRegToStackSlot() argument
178 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const loadRegFromStackSlot() argument
221 expandLoadStackGuard( MachineBasicBlock::iterator MI) const expandLoadStackGuard() argument
[all...] |
| H A D | ThumbRegisterInfo.cpp | 43 ThumbRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC, in getLargestLegalSuperClass() argument
54 ThumbRegisterInfo::getPointerRegClass(const MachineFunction &MF, in getPointerRegClass() argument
103 emitLoadConstPool( MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, unsigned DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred, unsigned PredReg, unsigned MIFlags) const emitLoadConstPool() argument
[all...] |
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/BPF/ |
| H A D | BPFInstrInfo.cpp | 45 void BPFInstrInfo::expandMEMCPY(MachineBasicBlock::iterator MI) const { in expandMEMCPY() argument
115 bool BPFInstrInfo::expandPostRAPseudo(MachineInstr &MI) const { in expandPostRAPseudo() argument
31 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const copyPhysReg() argument
124 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool IsKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const storeRegToStackSlot() argument
147 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const loadRegFromStackSlot() argument
164 analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const analyzeBranch() argument
219 insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, const DebugLoc &DL, int *BytesAdded) const insertBranch() argument
240 removeBranch(MachineBasicBlock &MBB, int *BytesRemoved) const removeBranch() argument
[all...] |
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/BPF/MCTargetDesc/ |
| H A D | BPFMCCodeEmitter.cpp | 86 getMachineOpValue(const MCInst &MI, const MCOperand &MO, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const getMachineOpValue() argument
118 encodeInstruction(const MCInst &MI, raw_ostream &OS, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const encodeInstruction() argument
158 getMemoryOpValue(const MCInst &MI, unsigned Op, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const getMemoryOpValue() argument
[all...] |
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| H A D | HexagonBitTracker.cpp | 89 BT::BitMask HexagonEvaluator::mask(unsigned Reg, unsigned Sub) const { in mask() argument
113 uint16_t HexagonEvaluator::getPhysRegBitWidth(unsigned Reg) const { in getPhysRegBitWidth() argument
132 composeWithSubRegIndex( const TargetRegisterClass &RC, unsigned Idx) const composeWithSubRegIndex() argument
176 size() const size() argument
178 operator [](unsigned n) const operator []() argument
[all...] |
| H A D | HexagonMachineFunctionInfo.h | 43 unsigned getSRetReturnReg() const { return SRetReturnReg; } in getSRetReturnReg() argument
55 bool isStartPacket(const MachineInstr* MI) const { in isStartPacket() argument
59 bool isEndPacket(const MachineInstr* MI) const { in isEndPacket() argument
64 bool hasClobberLR() const { return HasClobberLR; } in hasClobberLR() argument
66 bool hasEHReturn() const { retur argument
70 getStackAlignBaseVReg() const getStackAlignBaseVReg() argument
73 getStackAlignBasePhysReg() const getStackAlignBasePhysReg() argument
[all...] |
| H A D | HexagonTargetMachine.cpp | 227 HexagonTargetMachine::getSubtargetImpl(const Function &F) const { in getSubtargetImpl() argument
280 HexagonTargetMachine &getHexagonTargetMachine() const { in getHexagonTargetMachine() argument
[all...] |
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| H A D | HexagonMCExpr.cpp | 32 void HexagonMCExpr::visitUsedExpr(MCStreamer &Streamer) const { in visitUsedExpr() argument
36 MCFragment *llvm::HexagonMCExpr::findAssociatedFragment() const { in findAssociatedFragment() argument
77 void HexagonMCExpr::fixELFSymbolsInTLSFixups(MCAssembler &Asm) const { in fixELFSymbolsInTLSFixups() argument
26 evaluateAsRelocatableImpl(MCValue &Res, MCAsmLayout const *Layout, MCFixup const *Fixup) const evaluateAsRelocatableImpl() argument
82 getExpr() const getExpr() argument
89 mustExtend() const mustExtend() argument
94 mustNotExtend() const mustNotExtend() argument
96 s27_2_reloc() const s27_2_reloc() argument
109 printImpl(raw_ostream &OS, const MCAsmInfo *MAI) const printImpl() argument
117 signMismatch() const signMismatch() argument
[all...] |
| H A D | HexagonMCInstrInfo.h | 57 bool operator!=(PacketIterator const argument
[all...] |
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/ |
| H A D | LanaiRegisterInfo.cpp | 38 LanaiRegisterInfo::getCalleeSavedRegs(const MachineFunction * /*MF*/) const { in getCalleeSavedRegs() argument
42 BitVector LanaiRegisterInfo::getReservedRegs(const MachineFunction &MF) const { in getReservedRegs() argument
64 requiresRegisterScavenging( const MachineFunction & ) const requiresRegisterScavenging() argument
69 trackLivenessAfterRegAlloc( const MachineFunction & ) const trackLivenessAfterRegAlloc() argument
136 eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS) const eliminateFrameIndex() argument
249 hasBasePointer(const MachineFunction &MF) const hasBasePointer() argument
259 getRARegister() const getRARegister() argument
262 getFrameRegister(const MachineFunction & ) const getFrameRegister() argument
266 getBaseRegister() const getBaseRegister() argument
269 getCallPreservedMask(const MachineFunction & , CallingConv::ID ) const getCallPreservedMask() argument
[all...] |
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/MCTargetDesc/ |
| H A D | LanaiMCCodeEmitter.cpp | 109 getMachineOpValue( const MCInst &Inst, const MCOperand &MCOp, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &SubtargetInfo) const getMachineOpValue() argument
161 adjustPqBitsRmAndRrm(const MCInst &Inst, unsigned Value, const MCSubtargetInfo &STI) const adjustPqBitsRmAndRrm() argument
167 adjustPqBitsSpls(const MCInst &Inst, unsigned Value, const MCSubtargetInfo &STI) const adjustPqBitsSpls() argument
172 encodeInstruction( const MCInst &Inst, raw_ostream &Ostream, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &SubtargetInfo) const encodeInstruction() argument
185 getRiMemoryOpValue( const MCInst &Inst, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &SubtargetInfo) const getRiMemoryOpValue() argument
217 getRrMemoryOpValue( const MCInst &Inst, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &SubtargetInfo) const getRrMemoryOpValue() argument
256 getSplsOpValue(const MCInst &Inst, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &SubtargetInfo) const getSplsOpValue() argument
288 getBranchTargetOpValue( const MCInst &Inst, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &SubtargetInfo) const getBranchTargetOpValue() argument
[all...] |
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/MSP430/MCTargetDesc/ |
| H A D | MSP430MCCodeEmitter.cpp | 82 encodeInstruction(const MCInst &MI, raw_ostream &OS, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const encodeInstruction() argument
101 getMachineOpValue(const MCInst &MI, const MCOperand &MO, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const getMachineOpValue() argument
120 getMemOpValue(const MCInst &MI, unsigned Op, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const getMemOpValue() argument
152 getPCRelImmOpValue(const MCInst &MI, unsigned Op, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const getPCRelImmOpValue() argument
165 getCGImmOpValue(const MCInst &MI, unsigned Op, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const getCGImmOpValue() argument
184 getCCOpValue(const MCInst &MI, unsigned Op, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const getCCOpValue() argument
[all...] |
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/MSP430/ |
| H A D | MSP430FrameLowering.cpp | 28 bool MSP430FrameLowering::hasFP(const MachineFunction &MF) const { in hasFP() argument
36 bool MSP430FrameLowering::hasReservedCallFrame(const MachineFunction &MF) const { in hasReservedCallFrame() argument
40 emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const emitPrologue() argument
106 emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const emitEpilogue() argument
180 spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector<CalleeSavedInfo> &CSI, const TargetRegisterInfo *TRI) const spillCalleeSavedRegisters() argument
206 restoreCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, std::vector<CalleeSavedInfo> &CSI, const TargetRegisterInfo *TRI) const restoreCalleeSavedRegisters() argument
225 eliminateCallFramePseudoInstr( MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const eliminateCallFramePseudoInstr() argument
290 processFunctionBeforeFrameFinalized(MachineFunction &MF, RegScavenger *) const processFunctionBeforeFrameFinalized() argument
[all...] |
| H A D | MSP430InstrInfo.cpp | 132 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { in reverseBranchCondition() argument
36 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const storeRegToStackSlot() argument
63 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const loadRegFromStackSlot() argument
90 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const copyPhysReg() argument
106 removeBranch(MachineBasicBlock &MBB, int *BytesRemoved) const removeBranch() argument
163 isUnpredicatedTerminator(const MachineInstr &MI) const isUnpredicatedTerminator() argument
175 analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const analyzeBranch() argument
265 insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, const DebugLoc &DL, int *BytesAdded) const insertBranch() argument
300 getInstSizeInBytes(const MachineInstr &MI) const getInstSizeInBytes() argument
[all...] |
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsAsmBackend.cpp | 219 MipsAsmBackend::createObjectTargetWriter() const { in createObjectTargetWriter() argument
243 void MipsAsmBackend::applyFixup(const MCAssembler &Asm, const MCFixup &Fixup, in applyFixup() argument
303 Optional<MCFixupKind> MipsAsmBackend::getFixupKind(StringRef Name) const { in getFixupKind() argument
346 getFixupKindInfo(MCFixupKind Kind) const { in getFixupKindInfo() argument
521 writeNopData(raw_ostream &OS, uint64_t Count) const writeNopData() argument
576 isMicroMips(const MCSymbol *Sym) const isMicroMips() argument
[all...] |
| H A D | MipsInstPrinter.cpp | 74 void MipsInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const { in printRegName() argument
[all...] |
| H A D | MipsMCExpr.h | 64 MipsExprKind getKind() const { return Kind; } in getKind() argument
67 const MCExpr *getSubExpr() const { retur argument
85 isGpOff() const isGpOff() argument
[all...] |
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| H A D | Mips16FrameLowering.cpp | 42 emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const emitPrologue() argument
91 emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const emitEpilogue() argument
113 spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector<CalleeSavedInfo> &CSI, const TargetRegisterInfo *TRI) const spillCalleeSavedRegisters() argument
140 restoreCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, std::vector<CalleeSavedInfo> &CSI, const TargetRegisterInfo *TRI) const restoreCalleeSavedRegisters() argument
155 hasReservedCallFrame(const MachineFunction &MF) const hasReservedCallFrame() argument
162 determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS) const determineCalleeSaves() argument
[all...] |
| H A D | Mips16RegisterInfo.cpp | 42 requiresRegisterScavenging(const MachineFunction &MF) const requiresRegisterScavenging() argument
46 requiresFrameIndexScavenging(const MachineFunction &MF) const requiresFrameIndexScavenging() argument
51 useFPForScavengingIndex(const MachineFunction &MF) const useFPForScavengingIndex() argument
56 saveScavengerRegister(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MachineBasicBlock::iterator &UseMI, const TargetRegisterClass *RC, unsigned Reg) const saveScavengerRegister() argument
70 intRegClass(unsigned Size) const intRegClass() argument
75 eliminateFI(MachineBasicBlock::iterator II, unsigned OpNo, int FrameIndex, uint64_t StackSize, int64_t SPOffset) const eliminateFI() argument
[all...] |
| H A D | MipsCCState.h | 155 WasOriginalArgVectorFloat(unsigned ValNo) const WasOriginalArgVectorFloat() argument
158 WasOriginalRetVectorFloat(unsigned ValNo) const WasOriginalRetVectorFloat() argument
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| H A D | MipsISelLowering.h | 392 getAddrLocal(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, bool IsN32OrN64) const getAddrLocal() argument
411 getAddrGlobal(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, unsigned Flag, SDValue Chain, const MachinePointerInfo &PtrInfo) const getAddrGlobal() argument
424 getAddrGlobalLargeGOT(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, unsigned HiFlag, unsigned LoFlag, SDValue Chain, const MachinePointerInfo &PtrInfo) const getAddrGlobalLargeGOT() argument
443 getAddrNonPIC(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG) const getAddrNonPIC() argument
460 getAddrNonPICSym64(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG) const getAddrNonPICSym64() argument
487 getAddrGPRel(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, bool IsN64) const getAddrGPRel() argument
[all...] |
| H A D | MipsMachineFunction.h | 31 unsigned getSRetReturnReg() const { return SRetReturnReg; } in getSRetReturnReg() argument
42 int getVarArgsFrameIndex() const { return VarArgsFrameIndex; } in getVarArgsFrameIndex() argument
45 bool hasByvalArg() const { return HasByvalArg; } in hasByvalArg() argument
51 unsigned getIncomingArgSize() const { return IncomingArgSize; } in getIncomingArgSize() argument
53 bool callsEhReturn() const { return CallsEhReturn; } in callsEhReturn() argument
57 int getEhDataRegFI(unsigned Reg) const { return EhDataRegFI[Reg]; } in getEhDataRegFI() argument
66 bool isISR() const { retur argument
69 getISRRegFI(unsigned Reg) const getISRRegFI() argument
77 hasSaveS2() const hasSaveS2() argument
[all...] |
| H A D | MipsRegisterBankInfo.h | 141 wasVisited(const MachineInstr *MI) const wasVisited() argument
144 getRecordedTypeForInstr(const MachineInstr *MI) const getRecordedTypeForInstr() argument
157 getWaitingQueueFor(const MachineInstr *MI) const getWaitingQueueFor() argument
[all...] |
| H A D | MipsRegisterInfo.cpp | 47 MipsRegisterInfo::getPointerRegClass(const MachineFunction &MF, in getPointerRegClass() argument
67 MipsRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, in getRegPressureLimit() argument
93 MipsRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { in getCalleeSavedRegs() argument
124 getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const getCallPreservedMask() argument
150 getReservedRegs(const MachineFunction &MF) const getReservedRegs() argument
244 requiresRegisterScavenging(const MachineFunction &MF) const requiresRegisterScavenging() argument
249 trackLivenessAfterRegAlloc(const MachineFunction &MF) const trackLivenessAfterRegAlloc() argument
257 eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS) const eliminateFrameIndex() argument
281 getFrameRegister(const MachineFunction &MF) const getFrameRegister() argument
294 canRealignStack(const MachineFunction &MF) const canRealignStack() argument
[all...] |
| H A D | MipsSERegisterInfo.cpp | 44 requiresRegisterScavenging(const MachineFunction &MF) const { in requiresRegisterScavenging() argument
49 requiresFrameIndexScavenging(const MachineFunction &MF) const { in requiresFrameIndexScavenging() argument
54 MipsSERegisterInfo::intRegClass(unsigned Size) const { in intRegClass() argument
145 eliminateFI(MachineBasicBlock::iterator II, unsigned OpNo, int FrameIndex, uint64_t StackSize, int64_t SPOffset) const eliminateFI() argument
[all...] |