| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUTargetTransformInfo.cpp | 216 getHardwareNumberOfRegisters(bool Vec) const getHardwareNumberOfRegisters() argument
222 getNumberOfRegisters(bool Vec) const getNumberOfRegisters() argument
228 getRegisterBitWidth(bool Vector) const getRegisterBitWidth() argument
232 getMinVectorRegisterBitWidth() const getMinVectorRegisterBitWidth() argument
236 getLoadVectorFactor(unsigned VF, unsigned LoadSize, unsigned ChainSizeInBytes, VectorType *VecTy) const getLoadVectorFactor() argument
247 getStoreVectorFactor(unsigned VF, unsigned StoreSize, unsigned ChainSizeInBytes, VectorType *VecTy) const getStoreVectorFactor() argument
257 getLoadStoreVecRegBitWidth(unsigned AddrSpace) const getLoadStoreVecRegBitWidth() argument
276 isLegalToVectorizeMemChain(unsigned ChainSizeInBytes, unsigned Alignment, unsigned AddrSpace) const isLegalToVectorizeMemChain() argument
289 isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes, unsigned Alignment, unsigned AddrSpace) const isLegalToVectorizeLoadChain() argument
295 isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes, unsigned Alignment, unsigned AddrSpace) const isLegalToVectorizeStoreChain() argument
310 getTgtMemIntrinsic(IntrinsicInst *Inst, MemIntrinsicInfo &Info) const getTgtMemIntrinsic() argument
606 isSourceOfDivergence(const Value *V) const isSourceOfDivergence() argument
637 isAlwaysUniform(const Value *V) const isAlwaysUniform() argument
652 collectFlatAddressOperands(SmallVectorImpl<int> &OpIndexes, Intrinsic::ID IID) const collectFlatAddressOperands() argument
669 rewriteIntrinsicWithAddressSpace( IntrinsicInst *II, Value *OldV, Value *NewV) const rewriteIntrinsicWithAddressSpace() argument
730 areInlineCompatible(const Function *Caller, const Function *Callee) const areInlineCompatible() argument
871 getHardwareNumberOfRegisters(bool Vec) const getHardwareNumberOfRegisters() argument
875 getNumberOfRegisters(bool Vec) const getNumberOfRegisters() argument
879 getRegisterBitWidth(bool Vector) const getRegisterBitWidth() argument
883 getMinVectorRegisterBitWidth() const getMinVectorRegisterBitWidth() argument
887 getLoadStoreVecRegBitWidth(unsigned AddrSpace) const getLoadStoreVecRegBitWidth() argument
905 isLegalToVectorizeMemChain(unsigned ChainSizeInBytes, unsigned Alignment, unsigned AddrSpace) const isLegalToVectorizeMemChain() argument
914 isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes, unsigned Alignment, unsigned AddrSpace) const isLegalToVectorizeLoadChain() argument
920 isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes, unsigned Alignment, unsigned AddrSpace) const isLegalToVectorizeStoreChain() argument
[all...] |
| H A D | SIInstrInfo.h | 173 getRegisterInfo() const getRegisterInfo() argument
251 commuteOpcode(const MachineInstr &MI) const commuteOpcode() argument
337 isSALU(uint16_t Opcode) const isSALU() argument
345 isVALU(uint16_t Opcode) const isVALU() argument
353 isVMEM(uint16_t Opcode) const isVMEM() argument
361 isSOP1(uint16_t Opcode) const isSOP1() argument
369 isSOP2(uint16_t Opcode) const isSOP2() argument
377 isSOPC(uint16_t Opcode) const isSOPC() argument
385 isSOPK(uint16_t Opcode) const isSOPK() argument
393 isSOPP(uint16_t Opcode) const isSOPP() argument
401 isPacked(uint16_t Opcode) const isPacked() argument
409 isVOP1(uint16_t Opcode) const isVOP1() argument
417 isVOP2(uint16_t Opcode) const isVOP2() argument
425 isVOP3(uint16_t Opcode) const isVOP3() argument
433 isSDWA(uint16_t Opcode) const isSDWA() argument
441 isVOPC(uint16_t Opcode) const isVOPC() argument
449 isMUBUF(uint16_t Opcode) const isMUBUF() argument
457 isMTBUF(uint16_t Opcode) const isMTBUF() argument
465 isSMRD(uint16_t Opcode) const isSMRD() argument
475 isDS(uint16_t Opcode) const isDS() argument
485 isMIMG(uint16_t Opcode) const isMIMG() argument
493 isGather4(uint16_t Opcode) const isGather4() argument
514 isFLAT(uint16_t Opcode) const isFLAT() argument
522 isEXP(uint16_t Opcode) const isEXP() argument
530 isWQM(uint16_t Opcode) const isWQM() argument
538 isDisableWQM(uint16_t Opcode) const isDisableWQM() argument
546 isVGPRSpill(uint16_t Opcode) const isVGPRSpill() argument
554 isSGPRSpill(uint16_t Opcode) const isSGPRSpill() argument
562 isDPP(uint16_t Opcode) const isDPP() argument
570 isVOP3P(uint16_t Opcode) const isVOP3P() argument
578 isVINTRP(uint16_t Opcode) const isVINTRP() argument
586 isMAI(uint16_t Opcode) const isMAI() argument
594 isDOT(uint16_t Opcode) const isDOT() argument
614 sopkIsZext(uint16_t Opcode) const sopkIsZext() argument
624 isScalarStore(uint16_t Opcode) const isScalarStore() argument
632 isFixedSize(uint16_t Opcode) const isFixedSize() argument
640 hasFPClamp(uint16_t Opcode) const hasFPClamp() argument
648 getClampMask(const MachineInstr &MI) const getClampMask() argument
660 usesFPDPRounding(uint16_t Opcode) const usesFPDPRounding() argument
668 isFPAtomic(uint16_t Opcode) const isFPAtomic() argument
672 isVGPRCopy(const MachineInstr &MI) const isVGPRCopy() argument
680 hasVGPRUses(const MachineInstr &MI) const hasVGPRUses() argument
697 isInlineConstant(const APFloat &Imm) const isInlineConstant() argument
703 isInlineConstant(const MachineOperand &MO, const MCOperandInfo &OpInfo) const isInlineConstant() argument
710 isInlineConstant(const MachineInstr &MI, const MachineOperand &UseMO, const MachineOperand &DefMO) const isInlineConstant() argument
724 isInlineConstant(const MachineInstr &MI, unsigned OpIdx) const isInlineConstant() argument
729 isInlineConstant(const MachineInstr &MI, unsigned OpIdx, const MachineOperand &MO) const isInlineConstant() argument
746 isInlineConstant(const MachineOperand &MO) const isInlineConstant() argument
751 isLiteralConstant(const MachineOperand &MO, const MCOperandInfo &OpInfo) const isLiteralConstant() argument
756 isLiteralConstant(const MachineInstr &MI, int OpIdx) const isLiteralConstant() argument
809 getOpSize(uint16_t Opcode, unsigned OpNo) const getOpSize() argument
823 getOpSize(const MachineInstr &MI, unsigned OpNo) const getOpSize() argument
916 getNamedOperand(const MachineInstr &MI, unsigned OpName) const getNamedOperand() argument
922 getNamedImmOperand(const MachineInstr &MI, unsigned OpName) const getNamedImmOperand() argument
935 getMCOpcodeFromPseudo(unsigned Opcode) const getMCOpcodeFromPseudo() argument
[all...] |
| H A D | SIMachineScheduler.h | 110 unsigned getID() const { return ID; } in getID() argument
122 const std::vector<SIScheduleBlock*>& getPreds() const { return Preds; } in getPreds() argument
124 getSuccs() const { return Succs; } in getSuccs() argument
129 unsigned getNumHighLatencySuccessors() const { in getNumHighLatencySuccessors() argument
487 getVGPRSetID() const getVGPRSetID() argument
488 getSGPRSetID() const getSGPRSetID() argument
[all...] |
| H A D | SIPeepholeSDWA.cpp | 124 getTargetOperand() const getTargetOperand() argument
125 getReplacedOperand() const getReplacedOperand() argument
126 getParentInst() const getParentInst() argument
128 getMRI() const getMRI() argument
134 dump() const dump() argument
157 getSrcSel() const getSrcSel() argument
158 getAbs() const getAbs() argument
159 getNeg() const getNeg() argument
160 getSext() const getSext() argument
184 getDstSel() const getDstSel() argument
185 getDstUnused() const getDstUnused() argument
204 getPreservedOperand() const getPreservedOperand() argument
248 print(raw_ostream& OS) const print() argument
256 print(raw_ostream& OS) const print() argument
263 print(raw_ostream& OS) const print() argument
330 getSrcMods(const SIInstrInfo *TII, const MachineOperand *SrcOp) const getSrcMods() argument
518 foldToImm(const MachineOperand &Op) const foldToImm() argument
883 pseudoOpConvertToVOP2(MachineInstr &MI, const GCNSubtarget &ST) const pseudoOpConvertToVOP2() argument
940 isConvertibleToSDWA(MachineInstr &MI, const GCNSubtarget &ST) const isConvertibleToSDWA() argument
1176 legalizeScalarOperands(MachineInstr &MI, const GCNSubtarget &ST) const legalizeScalarOperands() argument
[all...] |
| H A D | SIRegisterInfo.cpp | 40 classifyPressureSet(unsigned PSetID, unsigned Reg, BitVector &PressureSets) const classifyPressureSet() argument
263 canRealignStack(const MachineFunction &MF) const canRealignStack() argument
276 requiresRegisterScavenging(const MachineFunction &Fn) const requiresRegisterScavenging() argument
287 requiresFrameIndexScavenging( const MachineFunction &MF) const requiresFrameIndexScavenging() argument
296 requiresFrameIndexReplacementScavenging( const MachineFunction &MF) const requiresFrameIndexReplacementScavenging() argument
302 requiresVirtualBaseRegisters( const MachineFunction &) const requiresVirtualBaseRegisters() argument
308 trackLivenessAfterRegAlloc(const MachineFunction &MF) const trackLivenessAfterRegAlloc() argument
313 getMUBUFInstrOffset(const MachineInstr *MI) const getMUBUFInstrOffset() argument
321 getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const getFrameIndexInstrOffset() argument
333 needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const needsFrameBaseReg() argument
342 materializeFrameBaseRegister(MachineBasicBlock *MBB, unsigned BaseReg, int FrameIdx, int64_t Offset) const materializeFrameBaseRegister() argument
377 resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, int64_t Offset) const resolveFrameIndex() argument
413 isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg, int64_t Offset) const isFrameOffsetLegal() argument
424 getPointerRegClass( const MachineFunction &MF, unsigned Kind) const getPointerRegClass() argument
614 buildSpillLoadStore(MachineBasicBlock::iterator MI, unsigned LoadStoreOp, int Index, unsigned ValueReg, bool IsKill, unsigned ScratchRsrcReg, unsigned ScratchOffsetReg, int64_t InstOffset, MachineMemOperand *MMO, RegScavenger *RS) const buildSpillLoadStore() argument
745 spillSGPR(MachineBasicBlock::iterator MI, int Index, RegScavenger *RS, bool OnlyToVGPR) const spillSGPR() argument
856 restoreSGPR(MachineBasicBlock::iterator MI, int Index, RegScavenger *RS, bool OnlyToVGPR) const restoreSGPR() argument
941 eliminateSGPRToVGPRSpillFrameIndex( MachineBasicBlock::iterator MI, int FI, RegScavenger *RS) const eliminateSGPRToVGPRSpillFrameIndex() argument
969 eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS) const eliminateFrameIndex() argument
1227 getRegAsmName(unsigned Reg) const getRegAsmName() argument
1233 getPhysRegClass(unsigned Reg) const getPhysRegClass() argument
1273 hasVGPRs(const TargetRegisterClass *RC) const hasVGPRs() argument
1679 getRegClassForReg(const MachineRegisterInfo &MRI, unsigned Reg) const getRegClassForReg() argument
1687 isVGPR(const MachineRegisterInfo &MRI, unsigned Reg) const isVGPR() argument
1694 isAGPR(const MachineRegisterInfo &MRI, unsigned Reg) const isAGPR() argument
1701 shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg, const TargetRegisterClass *NewRC, LiveIntervals &LIS) const shouldCoalesce() argument
1722 getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const getRegPressureLimit() argument
1738 getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const getRegPressureSetLimit() argument
1751 getRegUnitPressureSets(unsigned RegUnit) const getRegUnitPressureSets() argument
1759 getReturnAddressReg(const MachineFunction &MF) const getReturnAddressReg() argument
1765 getRegClassForSizeOnBank(unsigned Size, const RegisterBank &RB, const MachineRegisterInfo &MRI) const getRegClassForSizeOnBank() argument
1815 getConstrainedRegClassForOperand(const MachineOperand &MO, const MachineRegisterInfo &MRI) const getConstrainedRegClassForOperand() argument
1825 getVCC() const getVCC() argument
1830 getRegClass(unsigned RCID) const getRegClass() argument
1845 findReachingDef(unsigned Reg, unsigned SubReg, MachineInstr &Use, MachineRegisterInfo &MRI, LiveIntervals *LIS) const findReachingDef() argument
[all...] |
| H A D | SIWholeQuadMode.cpp | 533 requiresCorrectState(const MachineInstr &MI) const requiresCorrectState() argument
[all...] |
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/Disassembler/ |
| H A D | AMDGPUDisassembler.cpp | 241 tryDecodeInst(const uint8_t* Table, MCInst &MI, uint64_t Inst, uint64_t Address) const tryDecodeInst() argument
268 getInstruction(MCInst &MI, uint64_t &Size, ArrayRef<uint8_t> Bytes_, uint64_t Address, raw_ostream &CS) const getInstruction() argument
422 convertSDWAInst(MCInst &MI) const convertSDWAInst() argument
442 convertDPP8Inst(MCInst &MI) const convertDPP8Inst() argument
463 convertMIMGInst(MCInst &MI) const convertMIMGInst() argument
593 getRegClassName(unsigned RegClassID) const getRegClassName() argument
599 errOperand(unsigned V, const Twine& ErrMsg) const errOperand() argument
609 createRegOperand(unsigned int RegId) const createRegOperand() argument
614 createRegOperand(unsigned RegClassID, unsigned Val) const createRegOperand() argument
624 createSRegOperand(unsigned SRegClassID, unsigned Val) const createSRegOperand() argument
663 decodeOperand_VS_32(unsigned Val) const decodeOperand_VS_32() argument
667 decodeOperand_VS_64(unsigned Val) const decodeOperand_VS_64() argument
671 decodeOperand_VS_128(unsigned Val) const decodeOperand_VS_128() argument
675 decodeOperand_VSrc16(unsigned Val) const decodeOperand_VSrc16() argument
679 decodeOperand_VSrcV216(unsigned Val) const decodeOperand_VSrcV216() argument
683 decodeOperand_VGPR_32(unsigned Val) const decodeOperand_VGPR_32() argument
692 decodeOperand_VRegOrLds_32(unsigned Val) const decodeOperand_VRegOrLds_32() argument
696 decodeOperand_AGPR_32(unsigned Val) const decodeOperand_AGPR_32() argument
700 decodeOperand_AReg_128(unsigned Val) const decodeOperand_AReg_128() argument
704 decodeOperand_AReg_512(unsigned Val) const decodeOperand_AReg_512() argument
708 decodeOperand_AReg_1024(unsigned Val) const decodeOperand_AReg_1024() argument
712 decodeOperand_AV_32(unsigned Val) const decodeOperand_AV_32() argument
716 decodeOperand_AV_64(unsigned Val) const decodeOperand_AV_64() argument
720 decodeOperand_VReg_64(unsigned Val) const decodeOperand_VReg_64() argument
724 decodeOperand_VReg_96(unsigned Val) const decodeOperand_VReg_96() argument
728 decodeOperand_VReg_128(unsigned Val) const decodeOperand_VReg_128() argument
732 decodeOperand_VReg_256(unsigned Val) const decodeOperand_VReg_256() argument
736 decodeOperand_VReg_512(unsigned Val) const decodeOperand_VReg_512() argument
740 decodeOperand_SReg_32(unsigned Val) const decodeOperand_SReg_32() argument
747 decodeOperand_SReg_32_XM0_XEXEC( unsigned Val) const decodeOperand_SReg_32_XM0_XEXEC() argument
753 decodeOperand_SReg_32_XEXEC_HI( unsigned Val) const decodeOperand_SReg_32_XEXEC_HI() argument
759 decodeOperand_SRegOrLds_32(unsigned Val) const decodeOperand_SRegOrLds_32() argument
766 decodeOperand_SReg_64(unsigned Val) const decodeOperand_SReg_64() argument
770 decodeOperand_SReg_64_XEXEC(unsigned Val) const decodeOperand_SReg_64_XEXEC() argument
774 decodeOperand_SReg_128(unsigned Val) const decodeOperand_SReg_128() argument
778 decodeOperand_SReg_256(unsigned Val) const decodeOperand_SReg_256() argument
782 decodeOperand_SReg_512(unsigned Val) const decodeOperand_SReg_512() argument
786 decodeLiteralConstant() const decodeLiteralConstant() argument
907 getVgprClassId(const OpWidthTy Width) const getVgprClassId() argument
922 getAgprClassId(const OpWidthTy Width) const getAgprClassId() argument
940 getSgprClassId(const OpWidthTy Width) const getSgprClassId() argument
957 getTtmpClassId(const OpWidthTy Width) const getTtmpClassId() argument
974 getTTmpIdx(unsigned Val) const getTTmpIdx() argument
985 decodeSrcOp(const OpWidthTy Width, unsigned Val) const decodeSrcOp() argument
[all...] |
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARC/ |
| H A D | ARCISelLowering.cpp | 141 const char *ARCTargetLowering::getTargetNodeName(unsigned Opcode) const { in getTargetNodeName() argument
163 SDValue ARCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const { in LowerSELECT_CC() argument
197 SDValue ARCTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const { in LowerBR_CC() argument
210 SDValue ARCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const { in LowerJumpTable() argument
177 LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const LowerSIGN_EXTEND_INREG() argument
223 LowerCall(TargetLowering::CallLoweringInfo &CLI, SmallVectorImpl<SDValue> &InVals) const LowerCall() argument
431 LowerFormalArguments( SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const LowerFormalArguments() argument
446 LowerCallArguments( SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const LowerCallArguments() argument
592 CanLowerReturn( CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const CanLowerReturn() argument
605 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SDLoc &dl, SelectionDAG &DAG) const LowerReturn() argument
686 PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const PerformDAGCombine() argument
697 isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I) const isLegalAddressingMode() argument
705 mayBeEmittedAsTailCall(const CallInst *CI) const mayBeEmittedAsTailCall() argument
709 LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const LowerFRAMEADDR() argument
723 LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const LowerGlobalAddress() argument
747 LowerOperation(SDValue Op, SelectionDAG &DAG) const LowerOperation() argument
[all...] |
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| H A D | ARMInstructionSelector.cpp | 341 selectSimpleExtOpc(unsigned Opc, unsigned Size) const selectSimpleExtOpc() argument
357 selectLoadStoreOpCode(unsigned Opc, unsigned RegBank, unsigned Size) const selectLoadStoreOpCode() argument
494 putConstant(InsertInfo I, unsigned DestReg, unsigned Constant) const putConstant() argument
503 validOpRegPair(MachineRegisterInfo &MRI, unsigned LHSReg, unsigned RHSReg, unsigned ExpectedSize, unsigned ExpectedRegBankID) const validOpRegPair() argument
512 validReg(MachineRegisterInfo &MRI, unsigned Reg, unsigned ExpectedSize, unsigned ExpectedRegBankID) const validReg() argument
528 selectCmp(CmpConstants Helper, MachineInstrBuilder &MIB, MachineRegisterInfo &MRI) const selectCmp() argument
575 insertComparison(CmpConstants Helper, InsertInfo I, unsigned ResReg, ARMCC::CondCodes Cond, unsigned LHSReg, unsigned RHSReg, unsigned PrevRes) const insertComparison() argument
611 selectGlobal(MachineInstrBuilder &MIB, MachineRegisterInfo &MRI) const selectGlobal() argument
769 selectSelect(MachineInstrBuilder &MIB, MachineRegisterInfo &MRI) const selectSelect() argument
806 selectShift(unsigned ShiftOpc, MachineInstrBuilder &MIB) const selectShift() argument
815 renderVFPF32Imm( MachineInstrBuilder &NewInstBuilder, const MachineInstr &OldInst, int OpIdx) const renderVFPF32Imm() argument
828 renderVFPF64Imm( MachineInstrBuilder &NewInstBuilder, const MachineInstr &OldInst, int OpIdx) const renderVFPF64Imm() argument
[all...] |
| H A D | ARMLoadStoreOptimizer.cpp | 830 CreateLoadStoreDouble( MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, int Offset, unsigned Base, bool BaseKill, unsigned Opcode, ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL, ArrayRef<std::pair<unsigned, bool>> Regs, ArrayRef<MachineInstr*> Instrs) const CreateLoadStoreDouble() argument
[all...] |
| H A D | ARMParallelDSP.cpp | 161 bool is64Bit() const { return Root->getType()->isIntegerTy(64); } in is64Bit() argument
163 Type *getType() const { return Root->getType(); } in getType() argument
[all...] |
| H A D | ARMTargetTransformInfo.cpp | 52 bool ARMTTIImpl::areInlineCompatible(const Function *Caller, in areInlineCompatible() argument
1274 useReductionIntrinsic(unsigned Opcode, Type *Ty, TTI::ReductionFlags Flags) const useReductionIntrinsic() argument
[all...] |
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMAsmBackend.cpp | 50 Optional<MCFixupKind> ARMAsmBackend::getFixupKind(StringRef Name) const { in getFixupKind() argument
57 const MCFixupKindInfo &ARMAsmBackend::getFixupKindInfo(MCFixupKind Kind) const { in getFixupKindInfo() argument
218 bool ARMAsmBackend::mayNeedRelaxation(const MCInst &Inst, in mayNeedRelaxation() argument
195 getRelaxedOpcode(unsigned Op, const MCSubtargetInfo &STI) const getRelaxedOpcode() argument
232 reasonForFixupRelaxation(const MCFixup &Fixup, uint64_t Value) const reasonForFixupRelaxation() argument
311 fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value, const MCRelaxableFragment *DF, const MCAsmLayout &Layout) const fixupNeedsRelaxation() argument
317 relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI, MCInst &Res) const relaxInstruction() argument
348 writeNopData(raw_ostream &OS, uint64_t Count) const writeNopData() argument
414 adjustFixupValue(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target, uint64_t Value, bool IsResolved, MCContext &Ctx, const MCSubtargetInfo* STI) const adjustFixupValue() argument
1033 applyFixup(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target, MutableArrayRef<char> Data, uint64_t Value, bool IsResolved, const MCSubtargetInfo* STI) const applyFixup() argument
1096 generateCompactUnwindEncoding( ArrayRef<MCCFIInstruction> Instrs) const generateCompactUnwindEncoding() argument
[all...] |
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/AsmParser/ |
| H A D | AVRAsmParser.cpp | 98 getParser() const getParser() argument
99 getLexer() const getLexer() argument
129 addRegOperands(MCInst &Inst, unsigned N) const addRegOperands() argument
136 addExpr(MCInst &Inst, const MCExpr *Expr) const addExpr() argument
146 addImmOperands(MCInst &Inst, unsigned N) const addImmOperands() argument
155 addMemriOperands(MCInst &Inst, unsigned N) const addMemriOperands() argument
163 addImmCom8Operands(MCInst &Inst, unsigned N) const addImmCom8Operands() argument
171 isImmCom8() const isImmCom8() argument
179 isReg() const isReg() argument
180 isImm() const isImm() argument
181 isToken() const isToken() argument
182 isMem() const isMem() argument
183 isMemri() const isMemri() argument
185 getToken() const getToken() argument
190 getReg() const getReg() argument
196 getImm() const getImm() argument
240 getStartLoc() const getStartLoc() argument
241 getEndLoc() const getEndLoc() argument
243 print(raw_ostream &O) const print() argument
308 emit(MCInst &Inst, SMLoc const &Loc, MCStreamer &Out) const emit() argument
[all...] |
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| H A D | HexagonEarlyIfConv.cpp | 230 isPreheader(const MachineBasicBlock *B) const isPreheader() argument
341 hasEHLabel(const MachineBasicBlock *B) const hasEHLabel() argument
350 hasUncondBranch(const MachineBasicBlock *B) const hasUncondBranch() argument
361 isValidCandidate(const MachineBasicBlock *B) const isValidCandidate() argument
401 usesUndefVReg(const MachineInstr *MI) const usesUndefVReg() argument
417 isValid(const FlowPattern &FP) const isValid() argument
449 computePhiCost(const MachineBasicBlock *B, const FlowPattern &FP) const computePhiCost() argument
488 countPredicateDefs( const MachineBasicBlock *B) const countPredicateDefs() argument
505 isProfitable(const FlowPattern &FP) const isProfitable() argument
660 isPredicableStore(const MachineInstr *MI) const isPredicableStore() argument
684 isSafeToSpeculate(const MachineInstr *MI) const isSafeToSpeculate() argument
698 isPredicate(unsigned R) const isPredicate() argument
704 getCondStoreOpcode(unsigned Opc, bool IfTrue) const getCondStoreOpcode() argument
[all...] |
| H A D | HexagonSplitDouble.cpp | 145 isInduction(unsigned Reg, LoopRegMap &IRM) const isInduction() argument
154 isVolatileInstr(const MachineInstr *MI) const isVolatileInstr() argument
161 isFixedInstr(const MachineInstr *MI) const isFixedInstr() argument
315 profit(const MachineInstr *MI) const profit() argument
402 profit(unsigned Reg) const profit() argument
421 isProfitable(const USet &Part, LoopRegMap &IRM) const isProfitable() argument
[all...] |
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| H A D | HexagonMCInstrInfo.cpp | 34 bool HexagonMCInstrInfo::PredicateInfo::isPredicated() const { in isPredicated() argument
70 MCInst const &Hexagon::PacketIterator::operator*() const { in operator *() argument
76 bool Hexagon::PacketIterator::operator==(PacketIterator const &Other) const { in operator ==() argument
[all...] |
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/Disassembler/ |
| H A D | MipsDisassembler.cpp | 50 bool hasMips2() const { return STI.getFeatureBits()[Mips::FeatureMips2]; } in hasMips2() argument
51 bool hasMips3() const { return STI.getFeatureBits()[Mips::FeatureMips3]; } in hasMips3() argument
52 bool hasMips32() const { return STI.getFeatureBits()[Mips::FeatureMips32]; } in hasMips32() argument
54 bool hasMips32r6() const { in hasMips32r6() argument
58 bool isFP64() const { return STI.getFeatureBits()[Mips::FeatureFP64Bit]; } in isFP64() argument
60 bool isGP64() const { return STI.getFeatureBits()[Mips::FeatureGP64Bit]; } in isGP64() argument
62 bool isPTR64() const { return STI.getFeatureBits()[Mips::FeaturePTR64Bit]; } in isPTR64() argument
64 bool hasCnMips() const { return STI.getFeatureBits()[Mips::FeatureCnMips]; } in hasCnMips() argument
66 bool hasCnMipsP() const { retur argument
68 hasCOP3() const hasCOP3() argument
1219 getInstruction(MCInst &Instr, uint64_t &Size, ArrayRef<uint8_t> Bytes, uint64_t Address, raw_ostream &CStream) const getInstruction() argument
[all...] |
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| H A D | MipsAsmPrinter.cpp | 74 MipsTargetStreamer &MipsAsmPrinter::getTargetStreamer() const { in getTargetStreamer() argument
392 getCurrentABIString() const getCurrentABIString() argument
478 isBlockOnlyReachableByFallthrough(const MachineBasicBlock* MBB) const isBlockOnlyReachableByFallthrough() argument
836 emitInlineAsmStart() const emitInlineAsmStart() argument
852 emitInlineAsmEnd(const MCSubtargetInfo &StartInfo, const MCSubtargetInfo *EndInfo) const emitInlineAsmEnd() argument
1258 EmitDebugValue(const MCExpr *Value, unsigned Size) const EmitDebugValue() argument
1298 isLongBranchPseudo(int Opcode) const isLongBranchPseudo() argument
[all...] |
| H A D | MipsConstantIslandPass.cpp | 801 getOffsetOf(MachineInstr *MI) const getOffsetOf() argument
842 getUserOffset(CPUser &U) const getUserOffset() argument
[all...] |
| H A D | MipsSEISelDAGToDAG.cpp | 47 void MipsSEDAGToDAGISel::getAnalysisUsage(AnalysisUsage &AU) const { in getAnalysisUsage() argument
78 unsigned MipsSEDAGToDAGISel::getMSACtrlReg(const SDValue RegIdx) const { in getMSACtrlReg() argument
206 void MipsSEDAGToDAGISel::selectAddE(SDNode *Node, const SDLoc &DL) const { in selectAddE() argument
268 selectAddrFrameIndex(SDValue Addr, SDValue &Base, SDValue &Offset) const selectAddrFrameIndex() argument
281 selectAddrFrameIndexOffset( SDValue Addr, SDValue &Base, SDValue &Offset, unsigned OffsetBits, unsigned ShiftAmount = 0) const selectAddrFrameIndexOffset() argument
312 selectAddrRegImm(SDValue Addr, SDValue &Base, SDValue &Offset) const selectAddrRegImm() argument
362 selectAddrDefault(SDValue Addr, SDValue &Base, SDValue &Offset) const selectAddrDefault() argument
369 selectIntAddr(SDValue Addr, SDValue &Base, SDValue &Offset) const selectIntAddr() argument
375 selectAddrRegImm9(SDValue Addr, SDValue &Base, SDValue &Offset) const selectAddrRegImm9() argument
387 selectAddrRegImm11(SDValue Addr, SDValue &Base, SDValue &Offset) const selectAddrRegImm11() argument
399 selectAddrRegImm12(SDValue Addr, SDValue &Base, SDValue &Offset) const selectAddrRegImm12() argument
410 selectAddrRegImm16(SDValue Addr, SDValue &Base, SDValue &Offset) const selectAddrRegImm16() argument
421 selectIntAddr11MM(SDValue Addr, SDValue &Base, SDValue &Offset) const selectIntAddr11MM() argument
427 selectIntAddr12MM(SDValue Addr, SDValue &Base, SDValue &Offset) const selectIntAddr12MM() argument
433 selectIntAddr16MM(SDValue Addr, SDValue &Base, SDValue &Offset) const selectIntAddr16MM() argument
439 selectIntAddrLSL2MM(SDValue Addr, SDValue &Base, SDValue &Offset) const selectIntAddrLSL2MM() argument
461 selectIntAddrSImm10(SDValue Addr, SDValue &Base, SDValue &Offset) const selectIntAddrSImm10() argument
473 selectIntAddrSImm10Lsl1(SDValue Addr, SDValue &Base, SDValue &Offset) const selectIntAddrSImm10Lsl1() argument
484 selectIntAddrSImm10Lsl2(SDValue Addr, SDValue &Base, SDValue &Offset) const selectIntAddrSImm10Lsl2() argument
495 selectIntAddrSImm10Lsl3(SDValue Addr, SDValue &Base, SDValue &Offset) const selectIntAddrSImm10Lsl3() argument
511 selectVSplat(SDNode *N, APInt &Imm, unsigned MinSizeInBits) const selectVSplat() argument
551 selectVSplatCommon(SDValue N, SDValue &Imm, bool Signed, unsigned ImmBitSize) const selectVSplatCommon() argument
574 selectVSplatUimm1(SDValue N, SDValue &Imm) const selectVSplatUimm1() argument
579 selectVSplatUimm2(SDValue N, SDValue &Imm) const selectVSplatUimm2() argument
584 selectVSplatUimm3(SDValue N, SDValue &Imm) const selectVSplatUimm3() argument
590 selectVSplatUimm4(SDValue N, SDValue &Imm) const selectVSplatUimm4() argument
596 selectVSplatUimm5(SDValue N, SDValue &Imm) const selectVSplatUimm5() argument
602 selectVSplatUimm6(SDValue N, SDValue &Imm) const selectVSplatUimm6() argument
608 selectVSplatUimm8(SDValue N, SDValue &Imm) const selectVSplatUimm8() argument
614 selectVSplatSimm5(SDValue N, SDValue &Imm) const selectVSplatSimm5() argument
628 selectVSplatUimmPow2(SDValue N, SDValue &Imm) const selectVSplatUimmPow2() argument
659 selectVSplatMaskL(SDValue N, SDValue &Imm) const selectVSplatMaskL() argument
693 selectVSplatMaskR(SDValue N, SDValue &Imm) const selectVSplatMaskR() argument
714 selectVSplatUimmInvPow2(SDValue N, SDValue &Imm) const selectVSplatUimmInvPow2() argument
[all...] |
| H A D | MipsSubtarget.h | 231 isABI_FPXX() const isABI_FPXX() argument
242 hasMips1() const hasMips1() argument
243 hasMips2() const hasMips2() argument
244 hasMips3() const hasMips3() argument
245 hasMips4() const hasMips4() argument
246 hasMips5() const hasMips5() argument
247 hasMips4_32() const hasMips4_32() argument
248 hasMips4_32r2() const hasMips4_32r2() argument
249 hasMips32() const hasMips32() argument
253 hasMips32r2() const hasMips32r2() argument
257 hasMips32r3() const hasMips32r3() argument
261 hasMips32r5() const hasMips32r5() argument
265 hasMips32r6() const hasMips32r6() argument
269 hasMips64() const hasMips64() argument
270 hasMips64r2() const hasMips64r2() argument
271 hasMips64r3() const hasMips64r3() argument
272 hasMips64r5() const hasMips64r5() argument
273 hasMips64r6() const hasMips64r6() argument
275 hasCnMips() const hasCnMips() argument
276 hasCnMipsP() const hasCnMipsP() argument
278 isLittle() const isLittle() argument
279 isABICalls() const isABICalls() argument
280 isFPXX() const isFPXX() argument
281 isFP64bit() const isFP64bit() argument
282 useOddSPReg() const useOddSPReg() argument
283 noOddSPReg() const noOddSPReg() argument
284 isNaN2008() const isNaN2008() argument
285 inAbs2008Mode() const inAbs2008Mode() argument
286 isGP64bit() const isGP64bit() argument
287 isGP32bit() const isGP32bit() argument
288 getGPRSizeInBytes() const getGPRSizeInBytes() argument
289 isPTR64bit() const isPTR64bit() argument
290 isPTR32bit() const isPTR32bit() argument
291 hasSym32() const hasSym32() argument
294 isSingleFloat() const isSingleFloat() argument
295 isTargetELF() const isTargetELF() argument
296 hasVFPU() const hasVFPU() argument
297 inMips16Mode() const inMips16Mode() argument
298 inMips16ModeDefault() const inMips16ModeDefault() argument
305 inMips16HardFloat() const inMips16HardFloat() argument
308 inMicroMipsMode() const inMicroMipsMode() argument
309 inMicroMips32r6Mode() const inMicroMips32r6Mode() argument
312 hasDSP() const hasDSP() argument
313 hasDSPR2() const hasDSPR2() argument
314 hasDSPR3() const hasDSPR3() argument
315 hasMSA() const hasMSA() argument
316 disableMadd4() const disableMadd4() argument
317 hasEVA() const hasEVA() argument
318 hasMT() const hasMT() argument
319 hasCRC() const hasCRC() argument
320 hasVirt() const hasVirt() argument
321 hasGINV() const hasGINV() argument
322 useIndirectJumpsHazard() const useIndirectJumpsHazard() argument
325 useSmallSection() const useSmallSection() argument
327 hasStandardEncoding() const hasStandardEncoding() argument
329 useSoftFloat() const useSoftFloat() argument
331 useLongCalls() const useLongCalls() argument
333 useXGOT() const useXGOT() argument
335 enableLongBranchPass() const enableLongBranchPass() argument
340 hasExtractInsert() const hasExtractInsert() argument
341 hasMTHC1() const hasMTHC1() argument
343 allowMixed16_32() const allowMixed16_32() argument
346 os16() const os16() argument
348 isTargetNaCl() const isTargetNaCl() argument
356 getStackAlignment() const getStackAlignment() argument
369 systemSupportsUnalignedAccess() const systemSupportsUnalignedAccess() argument
[all...] |
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.cpp | 108 PPCInstrInfo::CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, in CreateTargetHazardRecognizer() argument
125 PPCInstrInfo::CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, in CreateTargetPostRAHazardRecognizer() argument
145 unsigned PPCInstrInfo::getInstrLatency(const InstrItineraryDat argument
175 getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const getOperandLatency() argument
233 isAssociativeAndCommutative(const MachineInstr &Inst) const isAssociativeAndCommutative() argument
267 getMachineCombinerPatterns( MachineInstr &Root, SmallVectorImpl<MachineCombinerPattern> &Patterns) const getMachineCombinerPatterns() argument
283 isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg, unsigned &SubIdx) const isCoalescableExtInstr() argument
298 isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const isLoadFromStackSlot() argument
318 isReallyTriviallyReMaterializable(const MachineInstr &MI, AliasAnalysis *AA) const isReallyTriviallyReMaterializable() argument
352 isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const isStoreToStackSlot() argument
368 commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const commuteInstructionImpl() argument
452 findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const findCommutedOpIndices() argument
468 insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const insertNoop() argument
488 getNoop(MCInst &NopInst) const getNoop() argument
495 analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const analyzeBranch() argument
670 removeBranch(MachineBasicBlock &MBB, int *BytesRemoved) const removeBranch() argument
702 insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, const DebugLoc &DL, int *BytesAdded) const insertBranch() argument
755 canInsertSelect(const MachineBasicBlock &MBB, ArrayRef<MachineOperand> Cond, unsigned TrueReg, unsigned FalseReg, int &CondCycles, int &TrueCycles, int &FalseCycles) const canInsertSelect() argument
792 insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &dl, unsigned DestReg, ArrayRef<MachineOperand> Cond, unsigned TrueReg, unsigned FalseReg) const insertSelect() argument
904 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const copyPhysReg() argument
1027 getStoreOpcodeForSpill(unsigned Reg, const TargetRegisterClass *RC) const getStoreOpcodeForSpill() argument
1114 getLoadOpcodeForSpill(unsigned Reg, const TargetRegisterClass *RC) const getLoadOpcodeForSpill() argument
1199 StoreRegToStackSlot( MachineFunction &MF, unsigned SrcReg, bool isKill, int FrameIdx, const TargetRegisterClass *RC, SmallVectorImpl<MachineInstr *> &NewMIs) const StoreRegToStackSlot() argument
1224 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const storeRegToStackSlot() argument
1255 LoadRegFromStackSlot(MachineFunction &MF, const DebugLoc &DL, unsigned DestReg, int FrameIdx, const TargetRegisterClass *RC, SmallVectorImpl<MachineInstr *> &NewMIs) const LoadRegFromStackSlot() argument
1277 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const loadRegFromStackSlot() argument
1314 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const reverseBranchCondition() argument
1324 FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, unsigned Reg, MachineRegisterInfo *MRI) const FoldImmediate() argument
[all...] |
| H A D | PPCTargetTransformInfo.cpp | 572 enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const enableMemCmpExpansion() argument
583 getNumberOfRegisters(unsigned ClassID) const getNumberOfRegisters() argument
594 getRegisterClassForType(bool Vector, Type *Ty) const getRegisterClassForType() argument
609 getRegisterClassName(unsigned ClassID) const getRegisterClassName() argument
622 getRegisterBitWidth(bool Vector) const getRegisterBitWidth() argument
635 getCacheLineSize() const getCacheLineSize() argument
651 getPrefetchDistance() const getPrefetchDistance() argument
[all...] |
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/AsmParser/ |
| H A D | SparcAsmParser.cpp | 101 bool is64Bit() const { in is64Bit() argument
259 isMEMrr() const isMEMrr() argument
260 isMEMri() const isMEMri() argument
261 isMembarTag() const isMembarTag() argument
263 isIntReg() const isIntReg() argument
267 isFloatReg() const isFloatReg() argument
271 isFloatOrDoubleReg() const isFloatOrDoubleReg() argument
276 isCoprocReg() const isCoprocReg() argument
280 getToken() const getToken() argument
290 getImm() const getImm() argument
295 getMemBase() const getMemBase() argument
300 getMemOffsetReg() const getMemOffsetReg() argument
305 getMemOff() const getMemOff() argument
333 addRegOperands(MCInst &Inst, unsigned N) const addRegOperands() argument
338 addImmOperands(MCInst &Inst, unsigned N) const addImmOperands() argument
344 addExpr(MCInst &Inst, const MCExpr *Expr) const addExpr() argument
354 addMEMrrOperands(MCInst &Inst, unsigned N) const addMEMrrOperands() argument
363 addMEMriOperands(MCInst &Inst, unsigned N) const addMEMriOperands() argument
372 addMembarTagOperands(MCInst &Inst, unsigned N) const addMembarTagOperands() argument
[all...] |