| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyPeephole.cpp | 97 const TargetRegisterClass *RegClass = MRI.getRegClass(Reg); in maybeRewriteToFallthrough() local
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| H A D | WebAssemblyRegStackify.cpp | 105 const auto *RegClass = MRI.getRegClass(MI->getOperand(0).getReg()); in convertImplicitDefToConstZero() local
609 const auto *RegClass = MRI.getRegClass(Reg); in moveAndTeeForMultiUse() local
[all...] |
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| H A D | RegisterClassInfo.h | 47 std::unique_ptr<RCInfo[]> RegClass; member in llvm::RegisterClassInfo
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| H A D | RegisterScavenging.h | 166 Register scavengeRegister(const TargetRegisterClass *RegClass, int SPAdj, in scavengeRegister() argument
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/ |
| H A D | Utils.cpp | 79 const TargetRegisterClass *RegClass = TII.getRegClass(II, OpIdx, &TRI, MF); in constrainOperandRegClass() local
30 constrainRegToClass(MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, unsigned Reg, const TargetRegisterClass &RegClass) constrainRegToClass() argument
40 constrainOperandRegClass( const MachineFunction &MF, const TargetRegisterInfo &TRI, MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, MachineInstr &InsertPt, const TargetRegisterClass &RegClass, const MachineOperand &RegMO, unsigned OpIdx) constrainOperandRegClass() argument
[all...] |
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| H A D | RenameIndependentSubregs.cpp | 134 const TargetRegisterClass *RegClass = MRI->getRegClass(Reg); in renameComponents() local
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| H A D | MachineRegisterInfo.cpp | 158 MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass, in createVirtualRegister() argument
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| H A D | LiveIntervals.cpp | 1671 const TargetRegisterClass *RegClass = MRI->getRegClass(Reg); in splitSeparateComponents() local
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| H A D | TargetInstrInfo.cpp | 52 short RegClass = MCID.OpInfo[OpNum].RegClass; in getRegClass() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| H A D | RDFRegisters.h | 136 const TargetRegisterClass *RegClass = nullptr; member
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| H A D | ARMBaseRegisterInfo.cpp | 814 const TargetRegisterClass *RegClass = in eliminateFrameIndex() local
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| H A D | ARMLoadStoreOptimizer.cpp | 581 unsigned ARMLoadStoreOpt::findFreeReg(const TargetRegisterClass &RegClass) { in findFreeReg() argument
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| H A D | ARMFrameLowering.cpp | 1533 const TargetRegisterClass *RegClass = TII.getRegClass(MCID, i, TRI, MF); in estimateRSStackSizeLimit() local
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| H A D | ARMBaseInstrInfo.cpp | 2433 const TargetRegisterClass *RegClass; local
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| H A D | ARMISelDAGToDAG.cpp | 1778 SDValue RegClass = in createGPRPairNode() local
1789 SDValue RegClass = in createSRegPairNode() local
1800 SDValue RegClass = CurDAG->getTargetConstant(ARM::QPRRegClassID, dl, in createDRegPairNode() local
1811 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, dl, in createQRegPairNode() local
1823 SDValue RegClass = in createQuadSRegsNode() local
1838 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, dl, createQuadDRegsNode() local
1853 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQQQPRRegClassID, dl, createQuadQRegsNode() local
[all...] |
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | ScheduleDAGRRList.cpp | 309 GetCostForDef(const ScheduleDAGSDNodes::RegDefIter &RegDefPos, const TargetLowering *TLI, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, unsigned &RegClass, unsigned &Cost, const MachineFunction &MF) GetCostForDef() argument
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| H A D | FastISel.cpp | 2026 const TargetRegisterClass *RegClass = in constrainOperandRegClass() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/MC/ |
| H A D | MCInstrDesc.h | 81 int16_t RegClass; member in llvm::MCOperandInfo
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| H A D | AArch64AsmPrinter.cpp | 706 const TargetRegisterClass *RegClass; in PrintAsmOperand() local
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| H A D | AArch64ISelLowering.cpp | 12846 SDValue RegClass = in createGPRPairNode() local
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| /third_party/mesa3d/src/amd/compiler/ |
| H A D | aco_ir.h | 308 struct RegClass { struct
339 constexpr RegClass(RC rc_) : rc(rc_) {} in RegClass() function
340 constexpr RegClass(RegType type, unsigned size) in RegClass() function
[all...] |
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelDAGToDAG.cpp | 588 int RegClass = Desc.OpInfo[OpIdx].RegClass; in getOperandRegClass() local
686 SDValue RegClass = CurDAG->getTargetConstant(RegClassID, DL, MVT::i32); in SelectBuildVector() local
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| H A D | SIInstrInfo.cpp | 763 const TargetRegisterClass *RegClass = MRI.getRegClass(DestReg); in materializeImmediate() local
[all...] |
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| H A D | X86ISelDAGToDAG.cpp | 4315 unsigned RegClass = getMaskRC(MaskVT); in tryVPTESTM() local
4353 unsigned RegClass = getMaskRC(ResVT); in tryVPTESTM() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/subzero/src/ |
| H A D | IceTargetLoweringMIPS32.cpp | 1568 const RegClassType RegClass = RegClassType( in addProlog() local
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