Searched refs:zn2 (Results 1 - 4 of 4) sorted by relevance
| /third_party/vixl/src/aarch64/ |
| H A D | assembler-sve-aarch64.cc | 5947 const ZRegister& zn2) { in splice_con()
5952 USE(zn2); in splice_con()
5954 VIXL_ASSERT(AreConsecutive(zn1, zn2)); in splice_con()
5955 VIXL_ASSERT(AreSameLaneSize(zd, zn1, zn2)); in splice_con()
8962 const ZRegister& zn2, in tbl()
8968 USE(zn2); in tbl()
8970 VIXL_ASSERT(AreConsecutive(zn1, zn2)); in tbl()
8971 VIXL_ASSERT(AreSameLaneSize(zd, zn1, zn2, zm)); in tbl()
8973 Emit(0x05202800 | SVESize(zd) | Rd(zd) | Rn(zn1) | Rn(zn2) | Rm(zm)); in tbl()
5944 splice_con(const ZRegister& zd, const PRegister& pg, const ZRegister& zn1, const ZRegister& zn2) splice_con() argument
8960 tbl(const ZRegister& zd, const ZRegister& zn1, const ZRegister& zn2, const ZRegister& zm) tbl() argument
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| H A D | simulator-aarch64.cc | 2197 SimVRegister& zn2 = ReadVRegister((instr->GetRn() + 1) % kNumberOfZRegisters); in Simulator() local
2203 ext(kFormatVnB, zd, zn, zn2, index); in Simulator()
13589 SimVRegister& zn2 = ReadVRegister((instr->GetRn() + 1) % kNumberOfZRegisters); in Simulator() local
13597 splice(vform, zd, pg, zn, zn2); in Simulator()
13708 SimVRegister& zn2 = ReadVRegister((instr->GetRn() + 1) % kNumberOfZRegisters); in Simulator() local
13716 tbl(vform, zd, zn, zn2, zm); in Simulator()
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| H A D | macro-assembler-aarch64.h | 7320 const ZRegister& zn2, in Tbl()
7324 tbl(zd, zn1, zn2, zm); in Tbl()
7318 Tbl(const ZRegister& zd, const ZRegister& zn1, const ZRegister& zn2, const ZRegister& zm) Tbl() argument
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| H A D | assembler-aarch64.h | 6618 const ZRegister& zn2,
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