| /third_party/vixl/test/aarch64/ |
| H A D | test-api-movprfx-aarch64.cc | 135 __ movprfx(z7, z15); in TEST()
136 __ clastb(z7.VnS(), p7, z7.VnS(), z7.VnS()); in TEST()
168 __ movprfx(z7, z2); in TEST()
169 __ lsr(z7.VnB(), p4.Merging(), z7.VnB(), z7.VnB()); in TEST()
183 __ movprfx(z7, z17); in TEST()
184 __ mad(z7 in TEST()
[all...] |
| H A D | test-disasm-sve-aarch64.cc | 424 COMPARE(asr(z7.VnH(), z24.VnH(), 16), "asr z7.h, z24.h, #16"); in TEST()
432 COMPARE(lsr(z7.VnH(), z24.VnH(), 15), "lsr z7.h, z24.h, #15"); in TEST()
440 COMPARE(lsl(z7.VnH(), z24.VnH(), 14), "lsl z7.h, z24.h, #14"); in TEST()
759 COMPARE_MACRO(Uqdecd(z7.VnD(), SVE_POW2, 1), "uqdecd z7.d, pow2"); in TEST()
760 COMPARE_MACRO(Uqdecd(z7.VnD(), SVE_VL1, 16), "uqdecd z7 in TEST()
[all...] |
| H A D | test-assembler-sve-aarch64.cc | 855 __ Clasta(z7.VnB(), p4, z7.VnB(), z0.VnB());
904 ASSERT_EQUAL_SVE(z7_expected, z7.VnD());
1012 __ Splice(z7.VnH(), p2, z29.VnH(), z30.VnH());
1060 ASSERT_EQUAL_SVE(z7_expected, z7.VnD());
1364 InsrHelper(&masm, z7.VnH(), z23_inputs);
1369 __ Eor(z7.VnH(), z7.VnH(), 0x0ff0);
1419 ASSERT_EQUAL_SVE(z7_expected, z7.VnH());
1820 __ Mov(z7, z
[all...] |
| H A D | test-api-aarch64.cc | 225 VIXL_CHECK(ZRegister(7).Is(z7)); in TEST()
613 VIXL_CHECK(!AreAliased(z6, z7)); in TEST()
614 VIXL_CHECK(!AreAliased(b6, z7)); in TEST()
615 VIXL_CHECK(!AreAliased(x7, z7)); in TEST()
637 VIXL_ASSERT(z7.H().Is(h7)); in TEST()
647 VIXL_CHECK(!z7.VnH().Is(h7)); in TEST()
652 VIXL_CHECK(!z7.VnH().Is(v7.H())); in TEST()
657 VIXL_CHECK(!z7.VnH().Is(z7.H())); in TEST()
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| H A D | test-trace-aarch64.cc | 2819 __ st3h(z5.VnH(), z6.VnH(), z7.VnH(), p4, SVEMemOperand(x0, 3, SVE_MUL_VL)); in GenerateTestSequenceSVE()
2820 __ st3w(z6.VnS(), z7.VnS(), z8.VnS(), p3, SVEMemOperand(x0, 3, SVE_MUL_VL)); in GenerateTestSequenceSVE()
2821 __ st3d(z7.VnD(), z8.VnD(), z9.VnD(), p4, SVEMemOperand(x0, x2, LSL, 3)); in GenerateTestSequenceSVE()
|
| /third_party/typescript/tests/baselines/reference/ |
| H A D | constDeclarations-es5.js | 2 const z7 = false;
8 var z7 = false;
variable
|
| H A D | typeArgInference2WithError.js | 8 var z7 = foo("abc", 5); // Error
variable
11 var z7 = foo("abc", 5); // Error
variable
|
| H A D | thisAndSuperInStaticMembers1(target=es2022).js | 22 static z7 = (() => { super.a = 0; })();
56 static z7 = (() => { super.a = 0; })();
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| H A D | thisAndSuperInStaticMembers1(target=esnext).js | 22 static z7 = (() => { super.a = 0; })();
56 static z7 = (() => { super.a = 0; })();
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| H A D | thisAndSuperInStaticMembers2(target=es2022).js | 22 static z7 = (() => { super.a = 0; })();
63 static { this.z7 = (() => { super.a = 0; })(); }
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| H A D | thisAndSuperInStaticMembers2(target=esnext).js | 22 static z7 = (() => { super.a = 0; })();
63 static { this.z7 = (() => { super.a = 0; })(); }
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| H A D | es6ExportEqualsInterop.js | 110 import z7 = require("function");
121 z7.a;
233 var z7 = require("function");
243 z7.a;
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| H A D | genericsManyTypeParameters.js | 28 x7: a619, y7: a27, z7: a37, a7: a47, b7: a57, c7: a67,
48 x7 , y7 , z7 , a7 , b7 , c7,
63 function Foo(x1, y1, z1, a1, b1, c1, x2, y2, z2, a2, b2, c2, x3, y3, z3, a3, b3, c3, x4, y4, z4, a4, b4, c4, x5, y5, z5, a5, b5, c5, x6, y6, z6, a6, b6, c6, x7, y7, z7, a7, b7, c7, x8, y8, z8, a8, b8, c8, x9, y9, z9, a9, b9, c9, x10, y12, z10, a10, b10, c10, x11, y13, z11, a11, b11, c11, x12, y14, z12, a12, b12, c12, x13, y15, z13, a13, b13, c13, x14, y16, z14, a14, b14, c14, x15, y17, z15, a15, b15, c15, x16, y18, z16, a16, b16, c16, x17, y19, z17, a17, b17, c17, x18, y10, z18, a18, b18, c18) {
70 x7, y7, z7, a7, b7, c7,
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| H A D | thisAndSuperInStaticMembers2(target=es2015).js | 22 static z7 = (() => { super.a = 0; })();
78 C.z7 = (() => { Reflect.set(_c, "a", 0, _b); })();
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| H A D | logicalAndOperatorStrictMode.js | 80 const z7 = z && n;
154 var z7 = z && n;
variable
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| H A D | thisAndSuperInStaticMembers1(target=es2015).js | 22 static z7 = (() => { super.a = 0; })();
153 Object.defineProperty(C, "z7", {
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| /third_party/ffmpeg/libavcodec/aarch64/ |
| H A D | simple_idct_neon.S | 46 #define z7 v0.H[6] define
85 smull\i v6.4S, \y2\l, z7
89 smlsl\i v18.4S, \y4\l, z7
113 smlal2 v5.4S, \y2\().8H, z7
120 smlal2 v17.4S, \y4\().8H, z7
186 smlal\i v5.4S, v29\l, z7
203 smlal\i v17.4S, v31\l, z7
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