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/third_party/node/deps/openssl/config/archs/linux-aarch64/asm/crypto/sha/
H A Dsha1-armv8.S26 ldp w20,w21,[x0]
46 ror w27,w20,#27
58 bic w25,w22,w20
59 and w26,w21,w20
64 ror w20,w20,#2
70 and w26,w20,w24
83 bic w25,w20,w23
86 add w20,w20,w2
[all...]
H A Dsha256-armv8.S89 ldp w20,w21,[x0] // load context
112 eor w19,w20,w21 // a^b, b^c in next round
114 ror w6,w20,#2
116 eor w17,w20,w20,ror#9
137 eor w28,w27,w20 // a^b, b^c in next round
145 eor w19,w19,w20 // Maj(a,b,c)
193 add w20,w20,w24 // d+=h
203 ror w16,w20,#
[all...]
/third_party/node/deps/openssl/config/archs/darwin64-arm64-cc/asm/crypto/sha/
H A Dsha1-armv8.S26 ldp w20,w21,[x0]
46 ror w27,w20,#27
58 bic w25,w22,w20
59 and w26,w21,w20
64 ror w20,w20,#2
70 and w26,w20,w24
83 bic w25,w20,w23
86 add w20,w20,w2
[all...]
H A Dsha256-armv8.S89 ldp w20,w21,[x0] // load context
112 eor w19,w20,w21 // a^b, b^c in next round
114 ror w6,w20,#2
116 eor w17,w20,w20,ror#9
137 eor w28,w27,w20 // a^b, b^c in next round
145 eor w19,w19,w20 // Maj(a,b,c)
193 add w20,w20,w24 // d+=h
203 ror w16,w20,#
[all...]
/third_party/node/deps/openssl/config/archs/darwin64-arm64-cc/asm_avx2/crypto/sha/
H A Dsha1-armv8.S26 ldp w20,w21,[x0]
46 ror w27,w20,#27
58 bic w25,w22,w20
59 and w26,w21,w20
64 ror w20,w20,#2
70 and w26,w20,w24
83 bic w25,w20,w23
86 add w20,w20,w2
[all...]
H A Dsha256-armv8.S89 ldp w20,w21,[x0] // load context
112 eor w19,w20,w21 // a^b, b^c in next round
114 ror w6,w20,#2
116 eor w17,w20,w20,ror#9
137 eor w28,w27,w20 // a^b, b^c in next round
145 eor w19,w19,w20 // Maj(a,b,c)
193 add w20,w20,w24 // d+=h
203 ror w16,w20,#
[all...]
/third_party/node/deps/openssl/config/archs/linux-aarch64/asm_avx2/crypto/sha/
H A Dsha1-armv8.S26 ldp w20,w21,[x0]
46 ror w27,w20,#27
58 bic w25,w22,w20
59 and w26,w21,w20
64 ror w20,w20,#2
70 and w26,w20,w24
83 bic w25,w20,w23
86 add w20,w20,w2
[all...]
H A Dsha256-armv8.S89 ldp w20,w21,[x0] // load context
112 eor w19,w20,w21 // a^b, b^c in next round
114 ror w6,w20,#2
116 eor w17,w20,w20,ror#9
137 eor w28,w27,w20 // a^b, b^c in next round
145 eor w19,w19,w20 // Maj(a,b,c)
193 add w20,w20,w24 // d+=h
203 ror w16,w20,#
[all...]
/third_party/node/deps/openssl/config/archs/linux-aarch64/asm/crypto/chacha/
H A Dchacha-armv8.S75 mov w20,w30
88 eor w20,w20,w7
92 ror w20,w20,#16
96 add w15,w15,w20
112 eor w20,w20,w7
116 ror w20,w20,#2
[all...]
/third_party/node/deps/openssl/config/archs/darwin64-arm64-cc/asm/crypto/chacha/
H A Dchacha-armv8.S75 mov w20,w30
88 eor w20,w20,w7
92 ror w20,w20,#16
96 add w15,w15,w20
112 eor w20,w20,w7
116 ror w20,w20,#2
[all...]
/third_party/node/deps/openssl/config/archs/darwin64-arm64-cc/asm_avx2/crypto/chacha/
H A Dchacha-armv8.S75 mov w20,w30
88 eor w20,w20,w7
92 ror w20,w20,#16
96 add w15,w15,w20
112 eor w20,w20,w7
116 ror w20,w20,#2
[all...]
/third_party/node/deps/openssl/config/archs/linux-aarch64/asm_avx2/crypto/chacha/
H A Dchacha-armv8.S75 mov w20,w30
88 eor w20,w20,w7
92 ror w20,w20,#16
96 add w15,w15,w20
112 eor w20,w20,w7
116 ror w20,w20,#2
[all...]
/third_party/vixl/test/aarch64/
H A Dtest-disasm-aarch64.cc282 COMPARE(add(w18, w19, Operand(w20, ASR, 5)), "add w18, w19, w20, asr #5"); in TEST()
308 COMPARE(sub(w18, w19, Operand(w20, ASR, 5)), "sub w18, w19, w20, asr #5"); in TEST()
338 COMPARE(add(x18, x19, Operand(x20, SXTB, 3)), "add x18, x19, w20, sxtb #3"); in TEST()
364 COMPARE(sub(x18, x19, Operand(x20, SXTB, 3)), "sub x18, x19, w20, sxtb #3"); in TEST()
390 COMPARE(sbcs(w18, w19, Operand(w20)), "sbcs w18, w19, w20"); in TEST()
495 COMPARE(cls(w20, w21), "cls w20, w2 in TEST()
[all...]
H A Dtest-assembler-aarch64.cc417 __ Mov(w20, Operand(w11, SXTB, 1)); in TEST()
5075 __ Add(w20, w4, -2000);
5093 ASSERT_EQUAL_32(398000, w20);
5928 ASSERT_EQUAL_32(NFlag, w20); // Negative and sign-extended
6121 __ Cmp(w20, Operand(w21, LSL, 1));
6133 __ Cmp(w20, Operand(w25, ASR, 2));
6165 __ Mov(w20, 0x2);
6173 __ Cmp(w20, Operand(w21, LSL, 1));
6268 __ Mov(w20, 0);
6270 __ Cmp(w20, Operan
[all...]
H A Dtest-trace-aarch64.cc112 __ crc32cb(w20, w21, w22); in GenerateTestSequenceBase()
146 __ eor(w19, w20, w21); in GenerateTestSequenceBase()
167 __ ldnp(w19, w20, MemOperand(x0)); in GenerateTestSequenceBase()
219 __ ldursh(w20, MemOperand(x0, 3)); in GenerateTestSequenceBase()
236 __ lsrv(w19, w20, w21); in GenerateTestSequenceBase()
260 __ ngc(w20, w21); in GenerateTestSequenceBase()
275 __ rev16(w20, w21); in GenerateTestSequenceBase()
293 __ stlrb(w20, MemOperand(x0)); in GenerateTestSequenceBase()
343 __ stxrh(w20, w21, MemOperand(x0)); in GenerateTestSequenceBase()
355 __ tst(w20, w2 in GenerateTestSequenceBase()
[all...]
H A Dtest-disasm-sve-aarch64.cc573 COMPARE_MACRO(Sqincw(x20, w20, SVE_POW2, 1), "sqincw x20, w20, pow2"); in TEST()
574 COMPARE_MACRO(Sqincd(x20, w20, SVE_VL1, 16), "sqincd x20, w20, vl1, mul #16"); in TEST()
575 COMPARE_MACRO(Sqinch(x20, w20, SVE_VL2, 15), "sqinch x20, w20, vl2, mul #15"); in TEST()
576 COMPARE_MACRO(Sqincw(x20, w20, SVE_VL16, 14), in TEST()
577 "sqincw x20, w20, vl16, mul #14"); in TEST()
578 COMPARE_MACRO(Sqincd(x20, w20, SVE_VL256, 8), in TEST()
579 "sqincd x20, w20, vl25 in TEST()
[all...]
H A Dtest-assembler-sve-aarch64.cc1623 __ Sqdecp(x20, p0.VnB(), w20);
2344 __ Mov(w20, 0xfffffffd);
2347 __ Whilele(p0.VnB(), w20, w21);
2349 __ Whilele(p1.VnH(), w20, w21);
2352 __ Mov(w20, 0xffffffff);
2355 __ Whilelt(p2.VnS(), w20, w21);
2357 __ Whilelt(p3.VnD(), w20, w21);
2360 __ Mov(w20, 0xfffffffd);
2363 __ Whilels(p4.VnB(), w20, w21);
2365 __ Whilels(p5.VnH(), w20, w2
[all...]
/third_party/node/deps/v8/src/codegen/loong64/
H A Dregister-loong64.h37 V(w16) V(w17) V(w18) V(w19) V(w20) V(w21) V(w22) V(w23) \
/third_party/node/deps/v8/src/codegen/mips64/
H A Dregister-mips64.h43 V(w16) V(w17) V(w18) V(w19) V(w20) V(w21) V(w22) V(w23) \
/third_party/node/deps/v8/src/codegen/mips/
H A Dregister-mips.h43 V(w16) V(w17) V(w18) V(w19) V(w20) V(w21) V(w22) V(w23) \
/third_party/ffmpeg/libpostproc/
H A Dpostprocess_template.c997 "movq "MANGLE(w20)", %%mm2 \n\t" // 32 in doVertDefFilter()
1048 NAMED_CONSTRAINTS_ADD(w05,w20) in doVertDefFilter()
3018 "movq "MANGLE(w20)", %%mm2 \n\t" // 32 in do_a_deblock()
3071 NAMED_CONSTRAINTS_ADD(w05,w20) in do_a_deblock()
H A Dpostprocess.c104 DECLARE_ASM_CONST(8, uint64_t, w20)= 0x0020002000200020LL;
/third_party/node/deps/v8/src/execution/mips64/
H A Dsimulator-mips64.h218 w20, enumerator
/third_party/node/deps/v8/src/execution/mips/
H A Dsimulator-mips.h218 w20, enumerator
/third_party/lzma/Asm/arm64/
H A DLzmaDecOpt.S176 #define rep0 w20

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