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Searched refs:vtx_info (Results 1 - 3 of 3) sorted by relevance

/third_party/mesa3d/src/amd/vulkan/
H A Dradv_nir_to_llvm.c427 const struct ac_data_format_info *vtx_info = ac_get_data_format_info(data_format); in load_vs_input() local
430 unsigned num_channels = MIN2(num_input_channels, vtx_info->num_channels); in load_vs_input()
448 unsigned chan_format = vtx_info->chan_format; in load_vs_input()
454 unsigned chan_offset = attrib_offset + chan * vtx_info->chan_byte_size; in load_vs_input()
H A Dradv_pipeline.c4214 const struct ac_data_format_info *vtx_info = ac_get_data_format_info(dfmt); in radv_lower_vs_input() local
4219 unsigned num_channels = MIN2(util_last_bit(mask), vtx_info->num_channels); in radv_lower_vs_input()
/third_party/mesa3d/src/amd/compiler/
H A Daco_instruction_selection.cpp5382 check_vertex_fetch_size(isel_context* ctx, const ac_data_format_info* vtx_info, unsigned offset,
5385 unsigned vertex_byte_size = vtx_info->chan_byte_size * channels;
5386 if (vtx_info->chan_byte_size != 4 && channels == 3)
5400 get_fetch_data_format(isel_context* ctx, const ac_data_format_info* vtx_info, unsigned offset,
5403 if (!vtx_info->chan_byte_size) {
5404 *channels = vtx_info->num_channels;
5405 return vtx_info->chan_format;
5409 if (!check_vertex_fetch_size(ctx, vtx_info, offset, binding_align, *channels)) {
5413 !check_vertex_fetch_size(ctx, vtx_info, offset, binding_align, new_channels)) {
5421 !check_vertex_fetch_size(ctx, vtx_info, offse
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