| /third_party/node/deps/v8/src/diagnostics/arm/ |
| H A D | disasm-arm.cc | 2172 // vsra.<type><size> Qd, Qm, shift in DecodeAdvancedSIMDDataProcessing()
2173 // vsra.<type><size> Dd, Dm, shift in DecodeAdvancedSIMDDataProcessing()
2181 "vsra.%s%d q%d, q%d, #%d", in DecodeAdvancedSIMDDataProcessing()
2187 "vsra.%s%d d%d, d%d, #%d", in DecodeAdvancedSIMDDataProcessing()
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| /third_party/node/deps/v8/src/codegen/riscv64/ |
| H A D | assembler-riscv64.h | 891 DEFINE_OPIVV(vsra, VSRA_FUNCT6)
892 DEFINE_OPIVX(vsra, VSRA_FUNCT6)
893 DEFINE_OPIVI(vsra, VSRA_FUNCT6)
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| H A D | assembler-riscv64.cc | 2761 DEFINE_OPIVV(vsra, VSRA_FUNCT6)
2762 DEFINE_OPIVX(vsra, VSRA_FUNCT6)
2763 DEFINE_OPIVI(vsra, VSRA_FUNCT6)
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| /third_party/node/deps/openssl/openssl/crypto/perlasm/ |
| H A D | s390x.pm | 72 vesrl vesrlb vesrlh vesrlf vesrlg vsl vslb vsldb vsra vsrab vsrl
1491 sub vsra { subroutine
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| /third_party/openssl/crypto/perlasm/ |
| H A D | s390x.pm | 72 vesrl vesrlb vesrlh vesrlf vesrlg vsl vslb vsldb vsra vsrab vsrl
1491 sub vsra { subroutine
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| /third_party/vixl/src/aarch32/ |
| H A D | assembler-aarch32.h | 5799 void vsra(Condition cond,
5804 void vsra(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) { in vsra() function in vixl::aarch32::Assembler
5805 vsra(al, dt, rd, rm, operand); in vsra()
5808 void vsra(Condition cond,
5813 void vsra(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) { in vsra() function in vixl::aarch32::Assembler
5814 vsra(al, dt, rd, rm, operand); in vsra()
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| H A D | disasm-aarch32.h | 2494 void vsra(Condition cond,
2500 void vsra(Condition cond,
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| H A D | assembler-aarch32.cc | 25891 void Assembler::vsra(Condition cond, in vsra() function in vixl::aarch32::Assembler
25930 Delegate(kVsra, &Assembler::vsra, cond, dt, rd, rm, operand); in vsra()
25933 void Assembler::vsra(Condition cond, in vsra() function in vixl::aarch32::Assembler
25972 Delegate(kVsra, &Assembler::vsra, cond, dt, rd, rm, operand); in vsra()
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| H A D | disasm-aarch32.cc | 6612 void Disassembler::vsra(Condition cond, in vsra() function in vixl::aarch32::Disassembler
6626 void Disassembler::vsra(Condition cond, in vsra() function in vixl::aarch32::Disassembler
[all...] |
| H A D | macro-assembler-aarch32.h | 12009 vsra(cond, dt, rd, rm, operand); in MacroAssembler()
12031 vsra(cond, dt, rd, rm, operand); in MacroAssembler()
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| /third_party/node/deps/v8/src/codegen/arm/ |
| H A D | assembler-arm.h | 948 void vsra(NeonDataType size, DwVfpRegister dst, DwVfpRegister src, int imm);
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| H A D | assembler-arm.cc | 4727 void Assembler::vsra(NeonDataType dt, DwVfpRegister dst, DwVfpRegister src, in vsra() function in v8::internal::Assembler
4730 // Dd = vsra(Dm, imm) SIMD shift right and accumulate. in vsra()
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| /third_party/node/deps/v8/src/codegen/s390/ |
| H A D | constants-s390.h | 533 V(vsra, VSRA, 0xE77E) /* type = VRR_C VECTOR SHIFT RIGHT ARITHMETIC */ \
|