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Searched refs:vs_output_param_offset (Results 1 - 11 of 11) sorted by relevance

/third_party/mesa3d/src/gallium/drivers/radeonsi/
H A Dsi_shader.c1734 uint8_t vs_output_param_offset[NUM_TOTAL_VARYING_SLOTS]) in si_nir_assign_param_offsets()
1758 vs_output_param_offset[sem.location] == AC_EXP_PARAM_DEFAULT_VAL_0000) { in si_nir_assign_param_offsets()
1764 vs_output_param_offset[sem.location] = (*num_param_exports)++; in si_nir_assign_param_offsets()
1773 vs_output_param_offset[i] = vs_output_param_offset[slot_remap[i]]; in si_nir_assign_param_offsets()
1793 STATIC_ASSERT(sizeof(shader->info.vs_output_param_offset[0]) == 1); in si_compile_shader()
1794 memset(shader->info.vs_output_param_offset, AC_EXP_PARAM_DEFAULT_VAL_0000, in si_compile_shader()
1795 sizeof(shader->info.vs_output_param_offset)); in si_compile_shader()
1803 /* This sets DEFAULT_VAL for constant outputs in vs_output_param_offset. */ in si_compile_shader()
1806 shader->info.vs_output_param_offset); in si_compile_shader()
1731 si_nir_assign_param_offsets(nir_shader *nir, const struct si_shader_info *info, int8_t slot_remap[NUM_TOTAL_VARYING_SLOTS], uint8_t *num_param_exports, uint64_t *output_param_mask, uint8_t vs_output_param_offset[NUM_TOTAL_VARYING_SLOTS]) si_nir_assign_param_offsets() argument
1892 ubyte *vs_output_param_offset = shader->info.vs_output_param_offset; si_compile_shader() local
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H A Dsi_shader_llvm_gs.c408 STATIC_ASSERT(sizeof(shader->info.vs_output_param_offset[0]) == 1); in si_generate_gs_copy_shader()
409 memset(shader->info.vs_output_param_offset, AC_EXP_PARAM_DEFAULT_VAL_0000, in si_generate_gs_copy_shader()
410 sizeof(shader->info.vs_output_param_offset)); in si_generate_gs_copy_shader()
423 shader->info.vs_output_param_offset[semantic] = shader->info.nr_param_exports++; in si_generate_gs_copy_shader()
H A Dsi_shader.h773 ubyte vs_output_param_offset[NUM_TOTAL_VARYING_SLOTS]; member
H A Dsi_shader_llvm_vs.c718 unsigned offset = shader->info.vs_output_param_offset[outputs[i].semantic]; in si_llvm_build_vs_exports()
/third_party/mesa3d/src/amd/vulkan/
H A Dradv_shader_info.c432 if (outinfo->vs_output_param_offset[idx] == AC_EXP_PARAM_UNDEFINED) in assign_outinfo_param()
433 outinfo->vs_output_param_offset[idx] = (*total_param_exports)++; in assign_outinfo_param()
556 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED, in radv_nir_shader_info_pass()
557 sizeof(outinfo->vs_output_param_offset)); in radv_nir_shader_info_pass()
H A Dradv_aco_shader_info.h51 ASSIGN_FIELD_CP(vs_output_param_offset); in radv_aco_convert_shader_vp_info()
H A Dradv_shader.h201 uint8_t vs_output_param_offset[VARYING_SLOT_MAX]; member
H A Dradv_nir_to_llvm.c887 radv_export_param(ctx, outinfo->vs_output_param_offset[slot_name], outputs[i].values, in radv_build_param_exports()
H A Dradv_pipeline.c6249 unsigned vs_offset = outinfo->vs_output_param_offset[slot]; in single_slot_to_ps_input()
6269 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_VAR0 + i]; in input_mask_to_ps_inputs()
/third_party/mesa3d/src/amd/compiler/
H A Daco_shader_info.h73 uint8_t vs_output_param_offset[VARYING_SLOT_MAX]; member
H A Daco_instruction_selection.cpp10889 const uint8_t *vs_output_param_offset =
10890 ctx->stage.has(SWStage::GS) ? ctx->program->info.vs.outinfo.vs_output_param_offset :
10891 ctx->stage.has(SWStage::TES) ? ctx->program->info.tes.outinfo.vs_output_param_offset :
10892 ctx->stage.has(SWStage::MS) ? ctx->program->info.ms.outinfo.vs_output_param_offset :
10893 ctx->program->info.vs.outinfo.vs_output_param_offset;
10895 assert(vs_output_param_offset);
10897 int offset = vs_output_param_offset[slot];

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