| /third_party/node/deps/v8/src/diagnostics/arm/ |
| H A D | disasm-arm.cc | 2322 Format(instr, "vrecpe.f32 'Qd, 'Qm"); in DecodeAdvancedSIMDTwoOrThreeRegisters()
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| /third_party/vixl/src/aarch32/ |
| H A D | assembler-aarch32.h | 5495 void vrecpe(Condition cond, DataType dt, DRegister rd, DRegister rm);
5496 void vrecpe(DataType dt, DRegister rd, DRegister rm) { in vrecpe() function in vixl::aarch32::Assembler
5497 vrecpe(al, dt, rd, rm); in vrecpe()
5500 void vrecpe(Condition cond, DataType dt, QRegister rd, QRegister rm);
5501 void vrecpe(DataType dt, QRegister rd, QRegister rm) { in vrecpe() function in vixl::aarch32::Assembler
5502 vrecpe(al, dt, rd, rm); in vrecpe()
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| H A D | disasm-aarch32.h | 2309 void vrecpe(Condition cond, DataType dt, DRegister rd, DRegister rm);
2311 void vrecpe(Condition cond, DataType dt, QRegister rd, QRegister rm);
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| H A D | assembler-aarch32.cc | 23867 void Assembler::vrecpe(Condition cond, in vrecpe() function in vixl::aarch32::Assembler
23896 Delegate(kVrecpe, &Assembler::vrecpe, cond, dt, rd, rm); in vrecpe()
23899 void Assembler::vrecpe(Condition cond, in vrecpe() function in vixl::aarch32::Assembler
23928 Delegate(kVrecpe, &Assembler::vrecpe, cond, dt, rd, rm); in vrecpe()
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| H A D | disasm-aarch32.cc | 6051 void Disassembler::vrecpe(Condition cond, in vrecpe() function in vixl::aarch32::Disassembler
6060 void Disassembler::vrecpe(Condition cond, in vrecpe() function in vixl::aarch32::Disassembler
[all...] |
| H A D | macro-assembler-aarch32.h | 11036 vrecpe(cond, dt, rd, rm); in MacroAssembler()
11053 vrecpe(cond, dt, rd, rm); in MacroAssembler()
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| /third_party/node/deps/v8/src/codegen/arm/ |
| H A D | assembler-arm.h | 950 // vrecpe and vrsqrte only support floating point lanes.
951 void vrecpe(QwNeonRegister dst, QwNeonRegister src);
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| H A D | assembler-arm.cc | 4736 void Assembler::vrecpe(QwNeonRegister dst, QwNeonRegister src) { in vrecpe() function in v8::internal::Assembler
4738 // Qd = vrecpe(Qm) SIMD reciprocal estimate. in vrecpe()
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| /third_party/node/deps/v8/src/compiler/backend/arm/ |
| H A D | code-generator-arm.cc | 2210 __ vrecpe(i.OutputSimd128Register(), i.InputSimd128Register(0)); in AssembleArchInstruction()
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