Searched refs:vlmul (Results 1 - 4 of 4) sorted by relevance
| /third_party/node/deps/v8/src/codegen/riscv64/ |
| H A D | assembler-riscv64.h | 662 static int32_t GenZimm(VSew vsew, Vlmul vlmul, TailAgnosticType tail = tu, in GenZimm() argument
664 return (mask << 7) | (tail << 6) | ((vsew & 0x7) << 3) | (vlmul & 0x7); in GenZimm()
1474 void vsetvli(Register rd, Register rs1, VSew vsew, Vlmul vlmul,
1477 void vsetivli(Register rd, uint8_t uimm, VSew vsew, Vlmul vlmul,
1480 inline void vsetvlmax(Register rd, VSew vsew, Vlmul vlmul, in vsetvlmax() argument
1483 vsetvli(rd, zero_reg, vsew, vlmul, tu, mu); in vsetvlmax()
1486 inline void vsetvl(VSew vsew, Vlmul vlmul, TailAgnosticType tail = tu, in vsetvl() argument
1488 vsetvli(zero_reg, zero_reg, vsew, vlmul, tu, mu); in vsetvl()
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| H A D | constants-riscv64.h | 1884 uint32_t vlmul = zimm & 0x7;
1885 return vlmul;
1909 uint32_t vlmul = this->RvvVlmul();
1910 switch (vlmul) {
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| H A D | assembler-riscv64.cc | 2869 void Assembler::vsetvli(Register rd, Register rs1, VSew vsew, Vlmul vlmul, in vsetvli() argument
2871 int32_t zimm = GenZimm(vsew, vlmul, tail, mask); in vsetvli()
2878 void Assembler::vsetivli(Register rd, uint8_t uimm, VSew vsew, Vlmul vlmul, in vsetivli() argument
2881 int32_t zimm = GenZimm(vsew, vlmul, tail, mask) & 0x3FF; in vsetivli()
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| /third_party/node/deps/v8/src/execution/riscv64/ |
| H A D | simulator-riscv64.h | 419 uint32_t vlmul = rvv_vlmul(); in rvv_lmul_s() local
420 switch (vlmul) { in rvv_lmul_s()
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