Home
last modified time | relevance | path

Searched refs:vldr (Results 1 - 24 of 24) sorted by relevance

/third_party/ffmpeg/libavcodec/arm/
H A Dmdct_vfp.S47 vldr d8, [TCOS, #trig_lo*4] @ s16,s17
48 vldr d9, [TCOS, #trig_hi*4] @ s18,s19
49 vldr s0, [IN, #in_hi*4 + 12]
50 vldr s1, [IN, #in_hi*4 + 4]
51 vldr s2, [IN, #in_lo*4 + 12]
52 vldr s3, [IN, #in_lo*4 + 4]
54 vldr d10, [TSIN, #trig_lo*4] @ s20,s21
55 vldr d11, [TSIN, #trig_hi*4] @ s22,s23
56 vldr s4, [IN, #in_lo*4]
57 vldr s
[all...]
H A Dfft_vfp.S55 vldr d0, [a1, #0*2*4] @ s0,s1 = z[0]
56 vldr d4, [a1, #1*2*4] @ s8,s9 = z[1]
57 vldr d1, [a1, #2*2*4] @ s2,s3 = z[2]
58 vldr d5, [a1, #3*2*4] @ s10,s11 = z[3]
92 vldr d4, [a1, #0 * 2*4]
93 vldr d6, [a1, #1 * 2*4]
94 vldr d5, [a1, #2 * 2*4]
95 vldr d7, [a1, #3 * 2*4]
97 vldr d12, [a1, #4 * 2*4]
99 vldr d1
[all...]
H A Dsynth_filter_vfp.S70 vldr d8, [P_SB, #OFFSET] @ d8 = SBUF_DAT
71 vldr d9, [P_SB, #OFFSET+8]
79 vldr d10, [P_SB, #OFFSET] @ d10 = SBUF_DAT_ALT
80 vldr d11, [P_SB, #OFFSET+8]
91 vldr d14, [P_WIN_UP, #OFFSET] @ d14 = WIN_UP_DAT
92 vldr d15, [P_WIN_UP, #OFFSET+8]
93 vldr d12, [P_WIN_DN, #OFFSET] @ d12 = WIN_DN_DAT
94 vldr d13, [P_WIN_DN, #OFFSET+8]
144 NOVFP vldr SCALE, [sp, #(16+6+3)*4]
180 vldr
[all...]
H A Dsynth_filter_neon.S43 NOVFP vldr s0, [sp, #12*4] @ scale
/third_party/optimized-routines/string/arm/
H A Dmemcpy.S87 vldr \vreg, [src, #\base]
89 vldr d0, [src, #\base + 8]
91 vldr d1, [src, #\base + 16]
93 vldr d2, [src, #\base + 24]
95 vldr \vreg, [src, #\base + prefetch_lines * 64 - 32]
97 vldr d0, [src, #\base + 40]
99 vldr d1, [src, #\base + 48]
101 vldr d2, [src, #\base + 56]
106 vldr \vreg, [src, #\base]
108 vldr d
[all...]
/third_party/node/deps/v8/src/compiler/backend/arm/
H A Dcode-generator-arm.cc1626 __ vldr(i.OutputFloatRegister(), i.InputOffset()); in AssembleArchInstruction()
1655 __ vldr(i.OutputDoubleRegister(), i.InputOffset()); in AssembleArchInstruction()
1766 __ vldr(i.OutputDoubleRegister(), MemOperand(fp, offset)); in AssembleArchInstruction()
1768 __ vldr(i.OutputFloatRegister(), MemOperand(fp, offset)); in AssembleArchInstruction()
3976 __ vldr(g.ToDoubleRegister(destination), src); in AssembleArchInstruction()
3992 __ vldr(temp, src); in AssembleArchInstruction()
3996 __ vldr(temp, src); in AssembleArchInstruction()
4105 __ vldr(src, dst); in AssembleArchInstruction()
4126 __ vldr(temp_0, dst); in AssembleArchInstruction()
4127 __ vldr(temp_ in AssembleArchInstruction()
[all...]
/third_party/vixl/src/aarch32/
H A Dassembler-aarch32.h4723 void vldr(Condition cond, DataType dt, DRegister rd, Location* location);
4729 void vldr(DataType dt, DRegister rd, Location* location) { in vldr() function in vixl::aarch32::Assembler
4730 vldr(al, dt, rd, location); in vldr()
4732 void vldr(DRegister rd, Location* location) { in vldr() function in vixl::aarch32::Assembler
4733 vldr(al, Untyped64, rd, location); in vldr()
4735 void vldr(Condition cond, DRegister rd, Location* location) { in vldr() function in vixl::aarch32::Assembler
4736 vldr(cond, Untyped64, rd, location); in vldr()
4739 void vldr(Condition cond,
4743 void vldr(DataType dt, DRegister rd, const MemOperand& operand) { in vldr() function in vixl::aarch32::Assembler
4744 vldr(a in vldr()
4746 void vldr(DRegister rd, const MemOperand& operand) { vldr() function in vixl::aarch32::Assembler
4749 void vldr(Condition cond, DRegister rd, const MemOperand& operand) { vldr() function in vixl::aarch32::Assembler
4759 void vldr(DataType dt, SRegister rd, Location* location) { vldr() function in vixl::aarch32::Assembler
4762 void vldr(SRegister rd, Location* location) { vldr() function in vixl::aarch32::Assembler
4765 void vldr(Condition cond, SRegister rd, Location* location) { vldr() function in vixl::aarch32::Assembler
4773 void vldr(DataType dt, SRegister rd, const MemOperand& operand) { vldr() function in vixl::aarch32::Assembler
4776 void vldr(SRegister rd, const MemOperand& operand) { vldr() function in vixl::aarch32::Assembler
4779 void vldr(Condition cond, SRegister rd, const MemOperand& operand) { vldr() function in vixl::aarch32::Assembler
[all...]
H A Dmacro-assembler-aarch32.cc2129 "The MacroAssembler does not convert vldr or vstr with a PC base " in Delegate()
2135 // vldr.32 s0, [r1, 12345]! will translate into in Delegate()
2137 // vldr.32 s0, [r1] in Delegate()
2151 // vldr.32 s0, [r1, 12345] will translate into in Delegate()
2153 // vldr.32 s0, [ip] in Delegate()
2167 // vldr.32 s0, [r1], imm32 will translate into in Delegate()
2168 // vldr.32 s0, [r1] in Delegate()
2202 "The MacroAssembler does not convert vldr or vstr with a PC base " in Delegate()
2208 // vldr.64 d0, [r1, 12345]! will translate into in Delegate()
2210 // vldr in Delegate()
[all...]
H A Ddisasm-aarch32.h1923 void vldr(Condition cond, DataType dt, DRegister rd, Location* location);
1925 void vldr(Condition cond,
1930 void vldr(Condition cond, DataType dt, SRegister rd, Location* location);
1932 void vldr(Condition cond,
H A Ddisasm-aarch32.cc5008 void Disassembler::vldr(Condition cond, in vldr() function in vixl::aarch32::Disassembler
5020 void Disassembler::vldr(Condition cond, in vldr() function in vixl::aarch32::Disassembler
5030 void Disassembler::vldr(Condition cond, in vldr() function in vixl::aarch32::Disassembler
5042 void Disassembler::vldr(Condition cond, in vldr() function in vixl::aarch32::Disassembler
[all...]
H A Dassembler-aarch32.cc19607 void Assembler::vldr(Condition cond, in vldr() function in vixl::aarch32::Assembler
19678 Delegate(kVldr, &Assembler::vldr, cond, dt, rd, location); in vldr()
19705 void Assembler::vldr(Condition cond, in vldr() function in vixl::aarch32::Assembler
19758 Delegate(kVldr, &Assembler::vldr, cond, dt, rd, operand); in vldr()
19761 void Assembler::vldr(Condition cond, in vldr() function in vixl::aarch32::Assembler
19832 Delegate(kVldr, &Assembler::vldr, cond, dt, rd, location); in vldr()
19859 void Assembler::vldr(Condition cond, in vldr() function in vixl::aarch32::Assembler
19912 Delegate(kVldr, &Assembler::vldr, cond, dt, rd, operand); in vldr()
H A Dmacro-assembler-aarch32.h832 vldr(cond, dt, rd, literal); in MacroAssembler()
865 vldr(cond, dt, rd, literal); in MacroAssembler()
8930 vldr(cond, dt, rd, operand); in MacroAssembler()
8957 vldr(cond, dt, rd, operand); in MacroAssembler()
/third_party/node/deps/v8/src/codegen/arm/
H A Dassembler-arm.h685 void vldr(const DwVfpRegister dst, const Register base, int offset,
687 void vldr(const DwVfpRegister dst, const MemOperand& src,
690 void vldr(const SwVfpRegister dst, const Register base, int offset,
692 void vldr(const SwVfpRegister dst, const MemOperand& src,
H A Dmacro-assembler-arm.cc1061 vldr(SwVfpRegister::from_code(dst_code), src); in CallRecordWriteStub()
1068 vldr(SwVfpRegister::from_code(dst_s_code), src); in CallRecordWriteStub()
1403 vldr(scratch, MemOperand(sp)); in CallRecordWriteStub()
1423 vldr(scratch, MemOperand(sp)); in CallRecordWriteStub()
H A Dassembler-arm.cc498 // vldr dd, [pc, #offset]
743 // vldr<cond> <Dd>, [pc +/- offset_10]. in IsVldrDPcImmediateOffset()
2425 void Assembler::vldr(const DwVfpRegister dst, const Register base, int offset, in vldr() function in v8::internal::Assembler
2461 void Assembler::vldr(const DwVfpRegister dst, const MemOperand& operand, in vldr() function in v8::internal::Assembler
2470 vldr(dst, scratch, 0, cond); in vldr()
2472 vldr(dst, operand.rn(), operand.offset(), cond); in vldr()
2476 void Assembler::vldr(const SwVfpRegister dst, const Register base, int offset, in vldr() function in v8::internal::Assembler
2510 void Assembler::vldr(const SwVfpRegister dst, const MemOperand& operand, in vldr() function in v8::internal::Assembler
2518 vldr(dst, scratch, 0, cond); in vldr()
2520 vldr(ds in vldr()
[all...]
/third_party/node/deps/openssl/openssl/crypto/chacha/asm/
H A Dchacha-armv4.pl786 vldr $t0#lo,[sp,#4*(16+0)] @ one
791 vldr $t1#lo,[sp,#4*(16+2)] @ two
828 vldr $t0#lo,[sp,#4*(16+4)] @ four
837 vldr $t0#lo,[sp,#4*(16+0)] @ one
/third_party/openssl/crypto/chacha/asm/
H A Dchacha-armv4.pl786 vldr $t0#lo,[sp,#4*(16+0)] @ one
791 vldr $t1#lo,[sp,#4*(16+2)] @ two
828 vldr $t0#lo,[sp,#4*(16+4)] @ four
837 vldr $t0#lo,[sp,#4*(16+0)] @ one
/third_party/ffmpeg/libavresample/arm/
H A Dresample_neon.S341 vldr s0, [sp, #12] /* frac */
/third_party/node/deps/openssl/config/archs/linux-armv4/asm_avx2/crypto/chacha/
H A Dchacha-armv4.S1105 vldr d24,[sp,#4*(16+0)] @ one
1110 vldr d26,[sp,#4*(16+2)] @ two
1147 vldr d24,[sp,#4*(16+4)] @ four
1156 vldr d24,[sp,#4*(16+0)] @ one
/third_party/node/deps/openssl/config/archs/linux-armv4/asm/crypto/chacha/
H A Dchacha-armv4.S1105 vldr d24,[sp,#4*(16+0)] @ one
1110 vldr d26,[sp,#4*(16+2)] @ two
1147 vldr d24,[sp,#4*(16+4)] @ four
1156 vldr d24,[sp,#4*(16+0)] @ one
/third_party/node/deps/v8/src/wasm/baseline/arm/
H A Dliftoff-assembler-arm.h356 assm->vldr(liftoff::GetFloatRegister(dst.fp()), src); in Load()
359 assm->vldr(dst.fp(), src); in Load()
4214 vldr(liftoff::GetFloatRegister(result_reg->fp()), MemOperand(sp));
4217 vldr(result_reg->fp(), MemOperand(sp));
4330 asm_->vldr(scratch, liftoff::GetStackSlot(slot.src_offset_));
/third_party/vixl/test/aarch32/
H A Dtest-assembler-aarch32.cc4134 // problem technically exists for the other loads, but vldr is particularly in TEST_T32()
4135 // badly affected because vldr cannot set the low bits in its offset mask, in TEST_T32()
4142 // vldr d0, [r8, #48] in TEST_T32()
4147 // vldr d0, [ip, #48] in TEST_T32()
6668 "vldr",
6670 vldr(al, Untyped64, d0, &label));
6673 "vldr",
6675 vldr(al, Untyped32, s0, &label));
6756 "vldr",
6758 vldr(a
[all...]
/third_party/node/deps/v8/src/builtins/arm/
H A Dbuiltins-arm.cc2904 __ vldr(double_scratch, input_operand); in Generate_DoubleToI()
/third_party/vixl/benchmarks/aarch32/
H A Dasm-disasm-speed-test.cc594 __ vldr(d7, &l_05f0); in Generate_4()
1424 __ vldr(s0, &l_0d24); in Generate_10()
1526 __ vldr(d7, &l_0d10); in Generate_11()

Completed in 232 milliseconds