Home
last modified time | relevance | path

Searched refs:vgpr (Results 1 - 24 of 24) sorted by relevance

/third_party/mesa3d/src/amd/compiler/
H A Daco_validate.cpp326 check(instr->definitions[0].getTemp().type() == RegType::vgpr, in validate_ir()
340 check(i == 1 || (op.isTemp() && op.regClass().type() == RegType::vgpr && in validate_ir()
347 check(i != 0 || (op.isTemp() && op.regClass().type() == RegType::vgpr), in validate_ir()
357 check(i != 2 || (op.isTemp() && op.regClass().type() == RegType::vgpr && in validate_ir()
416 check(instr->definitions[0].getTemp().type() == RegType::vgpr || in validate_ir()
421 instr->operands[0].regClass().type() == RegType::vgpr, in validate_ir()
431 if (instr->operands[0].getTemp().type() == RegType::vgpr) { in validate_ir()
433 check(def.regClass().type() == RegType::vgpr, in validate_ir()
449 (instr->definitions[i].getTemp().type() == RegType::vgpr && in validate_ir()
464 check(instr->definitions[0].getTemp().type() == RegType::vgpr, in validate_ir()
[all...]
H A Daco_instruction_selection_setup.cpp480 nir_dest_is_divergent(alu_instr->dest.dest) ? RegType::vgpr : RegType::sgpr; in init_context()
544 case nir_op_sdot_2x16_iadd_sat: type = RegType::vgpr; break; in init_context()
575 type = alu_instr->dest.dest.ssa.num_components == 2 ? RegType::vgpr : type; in init_context()
579 if (regclasses[alu_instr->src[i].src.ssa->index].type() == RegType::vgpr) in init_context()
580 type = RegType::vgpr; in init_context()
707 case nir_intrinsic_load_vector_arg_amd: type = RegType::vgpr; break; in init_context()
715 type = RegType::vgpr; in init_context()
732 type = nir_dest_is_divergent(intrinsic->dest) ? RegType::vgpr : RegType::sgpr; in init_context()
735 type = ctx->stage == fragment_fs ? RegType::vgpr : RegType::sgpr; in init_context()
740 if (regclasses[intrinsic->src[i].ssa->index].type() == RegType::vgpr) in init_context()
[all...]
H A Daco_ir.h304 vgpr, member in aco::RegType
333 /* these are used for WWM and spills to vgpr */
341 : rc((RC)((type == RegType::vgpr ? 1 << 5 : 0) | size)) in RegClass()
347 constexpr RegType type() const { return rc <= RC::s16 ? RegType::sgpr : RegType::vgpr; } in type()
370 return get(RegType::vgpr, bytes).as_linear(); in resize()
1845 constexpr RegisterDemand(const int16_t v, const int16_t s) noexcept : vgpr{v}, sgpr{s} {}
1846 int16_t vgpr = 0;
1851 return a.vgpr == b.vgpr && a.sgpr == b.sgpr;
1856 return vgpr > othe
[all...]
H A Daco_spill.cpp205 if (op.regClass().type() == RegType::vgpr && op.regClass().is_linear()) in next_uses_per_block()
415 if (op.regClass().type() == RegType::vgpr && op.regClass().is_linear()) in update_local_next_uses()
529 RegType type = RegType::vgpr; in init_live_in_vars()
532 if (type == RegType::vgpr && loop_demand.vgpr <= ctx.target_pressure.vgpr) in init_live_in_vars()
581 type = reg_pressure.vgpr > ctx.target_pressure.vgpr ? RegType::vgpr : RegType::sgpr; in init_live_in_vars()
618 if (pair.first.type() != RegType::vgpr) { in init_live_in_vars()
[all...]
H A Daco_lower_to_cssa.cpp173 idom = b.regClass().type() == RegType::vgpr ? ctx.program->blocks[idom].logical_idom in dominates()
197 std::vector<uint32_t>& preds = var.type() == RegType::vgpr in intersects()
351 pred = copy.op.regClass().type() == RegType::vgpr ? ctx.program->blocks[pred].logical_idom in try_coalesce_copy()
466 bool is_vgpr = cp.def.regClass().type() == RegType::vgpr; in emit_parallelcopies()
492 emit_copies_block(bld, ltg, RegType::vgpr); in emit_parallelcopies()
H A Daco_live_var_analysis.cpp130 register_demand[idx] = RegisterDemand(new_demand.vgpr, new_demand.sgpr); in process_live_temps_per_block()
415 if (new_demand.vgpr > vgpr_limit || new_demand.sgpr > sgpr_limit) { in update_vgpr_sgpr_demand()
421 get_vgpr_alloc(program, new_demand.vgpr) + program->config->num_shared_vgprs / 2; in update_vgpr_sgpr_demand()
429 program->max_reg_demand.vgpr = get_addr_vgpr_from_waves(program, program->num_waves); in update_vgpr_sgpr_demand()
H A Daco_reduce_assign.cpp60 Temp reduceTmp(0, RegClass(RegType::vgpr, maxSize).as_linear()); in setup_reduce_temp()
61 Temp vtmp(0, RegClass(RegType::vgpr, maxSize).as_linear()); in setup_reduce_temp()
H A Daco_lower_to_hw_instr.cpp391 RegClass rc = RegClass(RegType::vgpr, size); in emit_dpp_op()
431 RegClass rc = RegClass(RegType::vgpr, size); in emit_op()
433 Operand src0(src0_reg, RegClass(src0_reg.reg() >= 256 ? RegType::vgpr : RegType::sgpr, size)); in emit_op()
815 if (reduction_needs_last_op && dst.regClass().type() == RegType::vgpr) { in emit_reduction()
867 assert(input_data.regClass().type() == RegType::vgpr); in emit_gfx10_wave64_bpermute()
879 /* HI: Copy data from high lanes 32-63 to shared vgpr */ in emit_gfx10_wave64_bpermute()
886 /* LO: Copy data from low lanes 0-31 to shared vgpr */ in emit_gfx10_wave64_bpermute()
888 /* LO: bpermute shared vgpr (high lanes' data) */ in emit_gfx10_wave64_bpermute()
893 /* HI: bpermute shared vgpr (low lanes' data) */ in emit_gfx10_wave64_bpermute()
900 /* LO: Copy shared vgpr (hig in emit_gfx10_wave64_bpermute()
[all...]
H A Daco_instruction_selection.cpp275 return bld.copy(bld.def(RegType::vgpr, val.size()), val); in as_vgpr()
276 assert(val.type() == RegType::vgpr); in as_vgpr()
363 assert(dst_rc.type() == RegType::vgpr && it->second[idx].type() == RegType::sgpr); in emit_extract_vector()
396 rc = RegClass(RegType::vgpr, vec_src.bytes() / num_components).as_subdword(); in emit_split_vector()
418 assert(vec_src.type() == RegType::vgpr); in expand_vector()
422 Temp tmp_dst = bld.tmp(RegClass::get(RegType::vgpr, 2 * num_components)); in expand_vector()
443 RegClass src_rc = RegClass::get(RegType::vgpr, component_bytes); in expand_vector()
445 assert(dst.type() == RegType::vgpr || !src_rc.is_subdword()); in expand_vector()
563 RegClass rc = RegClass(RegType::vgpr, component_size).as_subdword(); in byte_align_vector()
570 if (dst.type() == RegType::vgpr) { in byte_align_vector()
[all...]
H A Daco_register_allocation.cpp178 if (rc.type() == RegType::vgpr) { in get_stride()
195 if (type == RegType::vgpr) { in get_reg_bounds()
196 return {PhysReg{256}, (unsigned)program->max_reg_demand.vgpr}; in get_reg_bounds()
420 PhysRegInterval regs = get_reg_bounds(ctx.program, vgprs ? RegType::vgpr : RegType::sgpr); in print_regs()
749 if (rc.type() == RegType::vgpr) { in adjust_max_used_regs()
896 (rc.type() == RegType::vgpr) ? (256 + ctx.max_used_vgpr) : ctx.max_used_sgpr; in get_reg_simple()
1429 if (type == RegType::vgpr && ctx.program->max_reg_demand.vgpr < ctx.vgpr_limit) { in increase_register_file()
1430 update_vgpr_sgpr_demand(ctx.program, RegisterDemand(ctx.program->max_reg_demand.vgpr + 1, in increase_register_file()
1433 update_vgpr_sgpr_demand(ctx.program, RegisterDemand(ctx.program->max_reg_demand.vgpr, in increase_register_file()
[all...]
H A Daco_ir.cpp230 if (gfx_level < GFX9 && !instr->operands[i].isOfType(RegType::vgpr)) in can_use_SDWA()
241 if (gfx_level < GFX9 && !instr->operands[0].isOfType(RegType::vgpr)) in can_use_SDWA()
343 if (instr->operands.size() > 1 && !instr->operands[1].isOfType(RegType::vgpr)) in can_use_DPP()
586 if (def.getTemp().type() == RegType::vgpr) in needs_exec_mask()
H A Daco_optimizer.cpp540 const bool vgpr = in pseudo_propagate_temp() local
543 [](const Definition& def) { return def.regClass().type() == RegType::vgpr; }); in pseudo_propagate_temp()
546 if (temp.type() == RegType::vgpr && !vgpr) in pseudo_propagate_temp()
640 return op.isTemp() && op.getTemp().type() == RegType::vgpr; in is_operand_vgpr()
1078 (tmp.type() == RegType::vgpr || ctx.program->gfx_level >= GFX9)) { in can_apply_extract()
1134 (tmp.type() == RegType::vgpr || ctx.program->gfx_level >= GFX9)) { in apply_extract()
1169 if (info.is_extract() && (info.instr->operands[0].getTemp().type() == RegType::vgpr || in check_sdwa_extract()
1321 if (is_copy_label(ctx, instr, info) && info.temp.type() == RegType::vgpr && in label_instruction()
1787 if (abs && neg && other.type() == RegType::vgpr) in label_instruction()
[all...]
H A Daco_scheduler.cpp1054 demand.vgpr += program->config->num_shared_vgprs / 2;
1067 else if (demand.vgpr >= 29)
1069 else if (demand.vgpr >= 25)
H A Daco_lower_phis.cpp326 Temp tmp = bld.tmp(RegClass(RegType::vgpr, phi_src.size())); in lower_subdword_phis()
H A Daco_print_ir.cpp850 fprintf(output, "\tdemand: %u vgpr, %u sgpr\n", demand.vgpr, demand.sgpr); in aco_print_block()
858 fprintf(output, "(%3u vgpr, %3u sgpr) ", demand.vgpr, demand.sgpr); in aco_print_block()
H A Daco_optimizer_postRA.cpp124 assert(def.regClass().type() != RegType::vgpr || def.physReg().reg() >= 256); in save_reg_writes()
H A Daco_statistics.cpp44 program->statistics[statistic_vgpr_presched] = presched_demand.vgpr; in collect_presched_stats()
H A Daco_insert_NOPs.cpp548 instr->operands[1].regClass().type() == RegType::vgpr && in handle_instruction_gfx6()
/third_party/mesa3d/src/gallium/drivers/radeonsi/
H A Dsi_shader_llvm_tess.c474 unsigned vgpr; in si_llvm_tcs_build_end() local
483 vgpr = 8 + GFX9_SGPR_TCS_OUT_LAYOUT + 1; in si_llvm_tcs_build_end()
490 vgpr = GFX6_TCS_NUM_USER_SGPR + 2; in si_llvm_tcs_build_end()
502 vgpr += 2; in si_llvm_tcs_build_end()
504 ret = LLVMBuildInsertValue(builder, ret, rel_patch_id, vgpr++, ""); in si_llvm_tcs_build_end()
505 ret = LLVMBuildInsertValue(builder, ret, invocation_id, vgpr++, ""); in si_llvm_tcs_build_end()
509 vgpr++; /* skip the tess factor LDS offset */ in si_llvm_tcs_build_end()
527 ret = LLVMBuildInsertValue(builder, ret, value, vgpr++, ""); in si_llvm_tcs_build_end()
530 ret = LLVMBuildInsertValue(builder, ret, tf_lds_offset, vgpr++, ""); in si_llvm_tcs_build_end()
561 unsigned vgpr in si_set_ls_return_value_for_tcs() local
[all...]
H A Dsi_shader_llvm_ps.c459 unsigned i, j, vgpr; in si_llvm_ps_build_end() local
507 vgpr = SI_SGPR_ALPHA_REF + 1; in si_llvm_ps_build_end()
516 ret = LLVMBuildInsertValue(builder, ret, tmp, vgpr++, ""); in si_llvm_ps_build_end()
518 vgpr += 2; in si_llvm_ps_build_end()
521 ret = LLVMBuildInsertValue(builder, ret, color[i][j], vgpr++, ""); in si_llvm_ps_build_end()
525 ret = LLVMBuildInsertValue(builder, ret, depth, vgpr++, ""); in si_llvm_ps_build_end()
527 ret = LLVMBuildInsertValue(builder, ret, stencil, vgpr++, ""); in si_llvm_ps_build_end()
529 ret = LLVMBuildInsertValue(builder, ret, samplemask, vgpr++, ""); in si_llvm_ps_build_end()
855 unsigned vgpr = ctx->args.num_sgprs_used; in si_llvm_build_ps_epilog() local
864 color[write_i][i] = LLVMGetParam(ctx->main_fn, vgpr in si_llvm_build_ps_epilog()
[all...]
H A Dsi_shader_llvm_gs.c75 unsigned vgpr = 8 + GFX9_GS_NUM_USER_SGPR; in si_set_es_return_value_for_gs() local
77 ret = si_insert_input_ret_float(ctx, ret, ctx->args.gs_vtx_offset[0], vgpr++); in si_set_es_return_value_for_gs()
78 ret = si_insert_input_ret_float(ctx, ret, ctx->args.gs_vtx_offset[1], vgpr++); in si_set_es_return_value_for_gs()
79 ret = si_insert_input_ret_float(ctx, ret, ctx->args.gs_prim_id, vgpr++); in si_set_es_return_value_for_gs()
80 ret = si_insert_input_ret_float(ctx, ret, ctx->args.gs_invocation_id, vgpr++); in si_set_es_return_value_for_gs()
81 ret = si_insert_input_ret_float(ctx, ret, ctx->args.gs_vtx_offset[2], vgpr++); in si_set_es_return_value_for_gs()
H A Dgfx10_shader_ngg.c1454 unsigned vgpr; in gfx10_ngg_culling_build_end() local
1457 vgpr = 8 + SI_SGPR_VS_VB_DESCRIPTOR_FIRST + shader->selector->info.num_vbos_in_user_sgprs * 4; in gfx10_ngg_culling_build_end()
1459 vgpr = 8 + GFX9_GS_NUM_USER_SGPR + 1; in gfx10_ngg_culling_build_end()
1462 vgpr = 8 + GFX9_GS_NUM_USER_SGPR; in gfx10_ngg_culling_build_end()
1466 ret = LLVMBuildInsertValue(builder, ret, ac_to_float(&ctx->ac, val), vgpr++, ""); in gfx10_ngg_culling_build_end()
1467 vgpr++; /* gs_vtx_offset[1] = offsets of vertices 2-3 */ in gfx10_ngg_culling_build_end()
1469 ret = si_insert_input_ret_float(ctx, ret, ctx->args.gs_prim_id, vgpr++); in gfx10_ngg_culling_build_end()
1470 ret = si_insert_input_ret_float(ctx, ret, ctx->args.gs_invocation_id, vgpr++); in gfx10_ngg_culling_build_end()
1471 vgpr++; /* gs_vtx_offset[2] = offsets of vertices 4-5 */ in gfx10_ngg_culling_build_end()
1478 ret = LLVMBuildInsertValue(builder, ret, ac_to_float(&ctx->ac, val), vgpr in gfx10_ngg_culling_build_end()
[all...]
/third_party/mesa3d/src/amd/llvm/
H A Dac_llvm_build.c451 LLVMValueRef vgpr = *pgpr; in ac_build_optimization_barrier() local
457 vgpr = LLVMBuildZExt(ctx->builder, vgpr, ctx->i32, ""); in ac_build_optimization_barrier()
459 vgpr_type = LLVMTypeOf(vgpr); in ac_build_optimization_barrier()
464 vgpr = LLVMBuildBitCast(builder, vgpr, LLVMVectorType(ctx->i32, vgpr_size / 4), ""); in ac_build_optimization_barrier()
465 vgpr0 = LLVMBuildExtractElement(builder, vgpr, ctx->i32_0, ""); in ac_build_optimization_barrier()
467 vgpr = LLVMBuildInsertElement(builder, vgpr, vgpr0, ctx->i32_0, ""); in ac_build_optimization_barrier()
468 vgpr in ac_build_optimization_barrier()
[all...]
/third_party/mesa3d/src/amd/compiler/tests/
H A Dhelpers.cpp114 RegType type = input_spec[0] == 'v' ? RegType::vgpr : RegType::sgpr; in setup_cs()

Completed in 41 milliseconds