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Searched refs:vform (Results 1 - 12 of 12) sorted by relevance

/third_party/node/deps/v8/src/codegen/arm64/
H A Dregister-arm64.cc12 VectorFormat VectorFormatHalfWidth(VectorFormat vform) { in VectorFormatHalfWidth() argument
13 DCHECK(vform == kFormat8H || vform == kFormat4S || vform == kFormat2D || in VectorFormatHalfWidth()
14 vform == kFormatH || vform == kFormatS || vform == kFormatD); in VectorFormatHalfWidth()
15 switch (vform) { in VectorFormatHalfWidth()
33 VectorFormat VectorFormatDoubleWidth(VectorFormat vform) { in VectorFormatDoubleWidth() argument
34 DCHECK(vform in VectorFormatDoubleWidth()
54 VectorFormatFillQ(VectorFormat vform) VectorFormatFillQ() argument
77 VectorFormatHalfWidthDoubleLanes(VectorFormat vform) VectorFormatHalfWidthDoubleLanes() argument
96 VectorFormatDoubleLanes(VectorFormat vform) VectorFormatDoubleLanes() argument
110 VectorFormatHalfLanes(VectorFormat vform) VectorFormatHalfLanes() argument
143 ScalarFormatFromFormat(VectorFormat vform) ScalarFormatFromFormat() argument
147 RegisterSizeInBytesFromFormat(VectorFormat vform) RegisterSizeInBytesFromFormat() argument
151 RegisterSizeInBitsFromFormat(VectorFormat vform) RegisterSizeInBitsFromFormat() argument
172 LaneSizeInBitsFromFormat(VectorFormat vform) LaneSizeInBitsFromFormat() argument
196 LaneSizeInBytesFromFormat(VectorFormat vform) LaneSizeInBytesFromFormat() argument
200 LaneSizeInBytesLog2FromFormat(VectorFormat vform) LaneSizeInBytesLog2FromFormat() argument
224 LaneCountFromFormat(VectorFormat vform) LaneCountFromFormat() argument
249 MaxLaneCountFromFormat(VectorFormat vform) MaxLaneCountFromFormat() argument
274 IsVectorFormat(VectorFormat vform) IsVectorFormat() argument
287 MaxIntFromFormat(VectorFormat vform) MaxIntFromFormat() argument
291 MinIntFromFormat(VectorFormat vform) MinIntFromFormat() argument
295 MaxUintFromFormat(VectorFormat vform) MaxUintFromFormat() argument
[all...]
H A Dregister-arm64.h296 VectorFormat VectorFormatHalfWidth(VectorFormat vform);
297 VectorFormat VectorFormatDoubleWidth(VectorFormat vform);
298 VectorFormat VectorFormatDoubleLanes(VectorFormat vform);
299 VectorFormat VectorFormatHalfLanes(VectorFormat vform);
301 VectorFormat VectorFormatHalfWidthDoubleLanes(VectorFormat vform);
303 VectorFormat VectorFormatFillQ(VectorFormat vform);
304 VectorFormat ScalarFormatFromFormat(VectorFormat vform);
305 V8_EXPORT_PRIVATE unsigned RegisterSizeInBitsFromFormat(VectorFormat vform);
306 unsigned RegisterSizeInBytesFromFormat(VectorFormat vform);
307 int LaneSizeInBytesFromFormat(VectorFormat vform);
[all...]
H A Dinstructions-arm64.cc389 static const VectorFormat vform[] = { in GetVectorFormat() local
393 DCHECK_LT(GetNEONFormat(format_map), arraysize(vform)); in GetVectorFormat()
394 return vform[GetNEONFormat(format_map)]; in GetVectorFormat()
/third_party/vixl/src/aarch64/
H A Dlogic-aarch64.cc185 void Simulator::ld1(VectorFormat vform, LogicVRegister dst, uint64_t addr) { in ld1() argument
186 dst.ClearForWrite(vform); in ld1()
187 for (int i = 0; i < LaneCountFromFormat(vform); i++) { in ld1()
188 LoadLane(dst, vform, i, addr); in ld1()
189 addr += LaneSizeInBytesFromFormat(vform); in ld1()
194 void Simulator::ld1(VectorFormat vform, in ld1() argument
198 LoadLane(dst, vform, index, addr); in ld1()
202 void Simulator::ld1r(VectorFormat vform, in ld1r() argument
208 dst.ClearForWrite(vform); in ld1r()
209 for (int i = 0; i < LaneCountFromFormat(vform); in ld1r()
219 ld1r(VectorFormat vform, LogicVRegister dst, uint64_t addr) ld1r() argument
224 ld2(VectorFormat vform, LogicVRegister dst1, LogicVRegister dst2, uint64_t addr1) ld2() argument
241 ld2(VectorFormat vform, LogicVRegister dst1, LogicVRegister dst2, int index, uint64_t addr1) ld2() argument
254 ld2r(VectorFormat vform, LogicVRegister dst1, LogicVRegister dst2, uint64_t addr) ld2r() argument
268 ld3(VectorFormat vform, LogicVRegister dst1, LogicVRegister dst2, LogicVRegister dst3, uint64_t addr1) ld3() argument
290 ld3(VectorFormat vform, LogicVRegister dst1, LogicVRegister dst2, LogicVRegister dst3, int index, uint64_t addr1) ld3() argument
307 ld3r(VectorFormat vform, LogicVRegister dst1, LogicVRegister dst2, LogicVRegister dst3, uint64_t addr) ld3r() argument
325 ld4(VectorFormat vform, LogicVRegister dst1, LogicVRegister dst2, LogicVRegister dst3, LogicVRegister dst4, uint64_t addr1) ld4() argument
352 ld4(VectorFormat vform, LogicVRegister dst1, LogicVRegister dst2, LogicVRegister dst3, LogicVRegister dst4, int index, uint64_t addr1) ld4() argument
373 ld4r(VectorFormat vform, LogicVRegister dst1, LogicVRegister dst2, LogicVRegister dst3, LogicVRegister dst4, uint64_t addr) ld4r() argument
395 st1(VectorFormat vform, LogicVRegister src, uint64_t addr) st1() argument
403 st1(VectorFormat vform, LogicVRegister src, int index, uint64_t addr) st1() argument
411 st2(VectorFormat vform, LogicVRegister src, LogicVRegister src2, uint64_t addr) st2() argument
426 st2(VectorFormat vform, LogicVRegister src, LogicVRegister src2, int index, uint64_t addr) st2() argument
437 st3(VectorFormat vform, LogicVRegister src, LogicVRegister src2, LogicVRegister src3, uint64_t addr) st3() argument
456 st3(VectorFormat vform, LogicVRegister src, LogicVRegister src2, LogicVRegister src3, int index, uint64_t addr) st3() argument
469 st4(VectorFormat vform, LogicVRegister src, LogicVRegister src2, LogicVRegister src3, LogicVRegister src4, uint64_t addr) st4() argument
492 st4(VectorFormat vform, LogicVRegister src, LogicVRegister src2, LogicVRegister src3, LogicVRegister src4, int index, uint64_t addr) st4() argument
507 cmp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, Condition cond) cmp() argument
551 cmp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, int imm, Condition cond) cmp() argument
562 cmptst(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) cmptst() argument
576 add(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) add() argument
606 add_uint(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, uint64_t value) add_uint() argument
635 addp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) addp() argument
649 sdiv(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) sdiv() argument
671 udiv(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) udiv() argument
691 mla(VectorFormat vform, LogicVRegister dst, const LogicVRegister& srca, const LogicVRegister& src1, const LogicVRegister& src2) mla() argument
703 mls(VectorFormat vform, LogicVRegister dst, const LogicVRegister& srca, const LogicVRegister& src1, const LogicVRegister& src2) mls() argument
715 mul(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) mul() argument
728 mul(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) mul() argument
739 smulh(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) smulh() argument
770 umulh(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) umulh() argument
801 mla(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) mla() argument
812 mls(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) mls() argument
822 sqdmull(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) sqdmull() argument
833 sqdmlal(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) sqdmlal() argument
844 sqdmlsl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) sqdmlsl() argument
855 sqdmulh(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) sqdmulh() argument
866 sqrdmulh(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) sqrdmulh() argument
877 sqrdmlah(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) sqrdmlah() argument
888 sqrdmlsh(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) sqrdmlsh() argument
915 pmul(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) pmul() argument
931 pmull(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) pmull() argument
950 pmull2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) pmull2() argument
968 sub(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) sub() argument
998 sub_uint(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, uint64_t value) sub_uint() argument
1027 and_(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) and_() argument
1039 orr(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) orr() argument
1051 orn(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) orn() argument
1063 eor(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) eor() argument
1075 bic(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) bic() argument
1087 bic(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, uint64_t imm) bic() argument
1104 bif(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) bif() argument
1120 bit(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) bit() argument
1136 bsl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src_mask, const LogicVRegister& src1, const LogicVRegister& src2) bsl() argument
1153 sminmax(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, bool max) sminmax() argument
1174 smax(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) smax() argument
1182 smin(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) smin() argument
1190 sminmaxp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, bool max) sminmaxp() argument
1221 smaxp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) smaxp() argument
1229 sminp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) sminp() argument
1237 addp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) addp() argument
1249 addv(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) addv() argument
1267 saddlv(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) saddlv() argument
1284 uaddlv(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) uaddlv() argument
1301 sminmaxv(VectorFormat vform, LogicVRegister dst, const LogicPRegister& pg, const LogicVRegister& src, bool max) sminmaxv() argument
1323 smaxv(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) smaxv() argument
1331 sminv(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) sminv() argument
1339 smaxv(VectorFormat vform, LogicVRegister dst, const LogicPRegister& pg, const LogicVRegister& src) smaxv() argument
1349 sminv(VectorFormat vform, LogicVRegister dst, const LogicPRegister& pg, const LogicVRegister& src) sminv() argument
1359 uminmax(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, bool max) uminmax() argument
1380 umax(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) umax() argument
1388 umin(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) umin() argument
1396 uminmaxp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, bool max) uminmaxp() argument
1427 umaxp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) umaxp() argument
1435 uminp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) uminp() argument
1443 uminmaxv(VectorFormat vform, LogicVRegister dst, const LogicPRegister& pg, const LogicVRegister& src, bool max) uminmaxv() argument
1465 umaxv(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) umaxv() argument
1473 uminv(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) uminv() argument
1481 umaxv(VectorFormat vform, LogicVRegister dst, const LogicPRegister& pg, const LogicVRegister& src) umaxv() argument
1491 uminv(VectorFormat vform, LogicVRegister dst, const LogicPRegister& pg, const LogicVRegister& src) uminv() argument
1501 shl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int shift) shl() argument
1512 sshll(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int shift) sshll() argument
1524 sshll2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int shift) sshll2() argument
1536 shll(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) shll() argument
1544 shll2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) shll2() argument
1552 ushll(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int shift) ushll() argument
1564 ushll2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int shift) ushll2() argument
1575 clast(VectorFormat vform, const LogicPRegister& pg, const LogicVRegister& src, int offset_from_last_active) clast() argument
1589 compact(VectorFormat vform, LogicVRegister dst, const LogicPRegister& pg, const LogicVRegister& src) compact() argument
1605 splice(VectorFormat vform, LogicVRegister dst, const LogicPRegister& pg, const LogicVRegister& src1, const LogicVRegister& src2) splice() argument
[all...]
H A Dsimulator-aarch64.h621 void SetActive(VectorFormat vform, int lane_index, bool value) { in SetActive() argument
622 int psize = LaneSizeInBytesFromFormat(vform); in SetActive()
630 bool IsActive(VectorFormat vform, int lane_index) const { in IsActive() argument
631 int psize = LaneSizeInBytesFromFormat(vform); in IsActive()
721 int64_t Int(VectorFormat vform, int index) const { in Int() argument
722 if (IsSVEFormat(vform)) register_.NotifyAccessAsZ(); in Int()
724 switch (LaneSizeInBitsFromFormat(vform)) { in Int()
744 uint64_t Uint(VectorFormat vform, int index) const { in Uint() argument
745 if (IsSVEFormat(vform)) register_.NotifyAccessAsZ(); in Uint()
747 switch (LaneSizeInBitsFromFormat(vform)) { in Uint()
767 UintArray(VectorFormat vform, uint64_t* dst) const UintArray() argument
774 UintLeftJustified(VectorFormat vform, int index) const UintLeftJustified() argument
778 IntLeftJustified(VectorFormat vform, int index) const IntLeftJustified() argument
785 SetInt(VectorFormat vform, int index, int64_t value) const SetInt() argument
806 SetIntArray(VectorFormat vform, const int64_t* src) const SetIntArray() argument
813 SetUint(VectorFormat vform, int index, uint64_t value) const SetUint() argument
834 SetUintArray(VectorFormat vform, const uint64_t* src) const SetUintArray() argument
852 SetFloat(VectorFormat vform, int index, T value) const SetFloat() argument
911 SignedSaturate(VectorFormat vform) SignedSaturate() argument
923 UnsignedSaturate(VectorFormat vform) UnsignedSaturate() argument
942 Round(VectorFormat vform) Round() argument
951 Uhalve(VectorFormat vform) Uhalve() argument
967 Halve(VectorFormat vform) Halve() argument
1036 LogicSVEAddressVector(uint64_t base, const SimVRegister* vector, VectorFormat vform, SVEOffsetModifier mod = NO_SVE_OFFSET_MODIFIER, int shift = 0) LogicSVEAddressVector() argument
[all...]
H A Dsimulator-aarch64.cc841 void Simulator::ExtractFromSimVRegister(VectorFormat vform, in Simulator()
847 vform, in Simulator()
1203 VectorFormat vform) { in Simulator()
1204 switch (vform) { in Simulator()
1247 VectorFormat vform) { in Simulator()
1248 switch (vform) { in Simulator()
2141 VectorFormat vform = instr->GetSVEVectorFormat(); in Simulator() local
2149 match(vform, pd, zn, zm, /* negate_match = */ false); in Simulator()
2152 match(vform, pd, zn, zm, /* negate_match = */ true); in Simulator()
2158 PredTest(vform, p in Simulator()
1202 GetPrintRegisterFormat( VectorFormat vform) Simulator() argument
1246 GetPrintRegisterFormatFP( VectorFormat vform) Simulator() argument
2162 VectorFormat vform = instr->GetSVEVectorFormat(); Simulator() local
2233 VectorFormat vform = instr->GetSVEVectorFormat(); Simulator() local
2252 VectorFormat vform = instr->GetSVEVectorFormat(); Simulator() local
2276 VectorFormat vform = instr->GetSVEVectorFormat(); Simulator() local
2306 VectorFormat vform = instr->GetSVEVectorFormat(); Simulator() local
2458 VectorFormat vform = instr->GetSVEVectorFormat(); Simulator() local
2482 VectorFormat vform = instr->GetSVEVectorFormat(); Simulator() local
2506 VectorFormat vform = instr->GetSVEVectorFormat(); Simulator() local
2523 VectorFormat vform = instr->GetSVEVectorFormat(); Simulator() local
2571 VectorFormat vform = instr->GetSVEVectorFormat(); Simulator() local
2620 VectorFormat vform = SVEFormatFromLaneSizeInBytesLog2(lane_size); Simulator() local
2648 VectorFormat vform = SVEFormatFromLaneSizeInBytesLog2(lane_size); Simulator() local
2736 VectorFormat vform = instr->GetSVEVectorFormat(); Simulator() local
2814 VectorFormat vform = instr->GetSVEVectorFormat(); Simulator() local
2874 VectorFormat vform = VectorFormatHalfWidth(vform_src); Simulator() local
2927 VectorFormat vform = SVEFormatFromLaneSizeInBytesLog2(lane_size + 1); Simulator() local
2956 VectorFormat vform = instr->GetSVEVectorFormat(); Simulator() local
3113 VectorFormat vform = instr->GetSVEVectorFormat(); Simulator() local
3133 VectorFormat vform = (instr->ExtractBit(22) == 0) ? kFormatVnS : kFormatVnD; Simulator() local
3160 VectorFormat vform = instr->GetSVEVectorFormat(); Simulator() local
3182 VectorFormat vform = instr->GetSVEVectorFormat(); Simulator() local
3224 VectorFormat vform = SVEFormatFromLaneSizeInBytesLog2(lane_size); Simulator() local
3246 VectorFormat vform = instr->GetSVEVectorFormat(); Simulator() local
3309 VectorFormat vform = instr->GetSVEVectorFormat(); Simulator() local
3339 VectorFormat vform = kFormatVnD; Simulator() local
3375 VectorFormat vform = instr->GetSVEVectorFormat(); Simulator() local
3414 VectorFormat vform = instr->GetSVEVectorFormat(); Simulator() local
3453 VectorFormat vform = instr->GetSVEVectorFormat(); Simulator() local
3483 VectorFormat vform = instr->GetSVEVectorFormat(); Simulator() local
3518 VectorFormat vform = SVEFormatFromLaneSizeInBytesLog2(lane_size); Simulator() local
3555 VectorFormat vform = SVEFormatFromLaneSizeInBytesLog2(lane_size); Simulator() local
3562 VectorFormat vform = instr->GetSVEVectorFormat(); Simulator() local
6331 VectorFormat vform; Simulator() local
6477 VectorFormat vform; Simulator() local
8002 VectorFormat vform = instr->GetNEONQ() ? kFormat4S : kFormat2S; Simulator() local
8033 VectorFormat vform = nfd.GetVectorFormat(&map); Simulator() local
8077 VectorFormat vform = instr->GetNEONQ() ? kFormat8H : kFormat4H; Simulator() local
8097 VectorFormat vform = instr->GetNEONQ() ? kFormat4S : kFormat2S; Simulator() local
8127 VectorFormat vform = nfd.GetVectorFormat(); Simulator() local
8647 VectorFormat vform = kFormatUndefined; Simulator() local
9641 VectorFormat vform = kFormatVnD; Simulator() local
9698 VectorFormat vform = SVEFormatFromLaneSizeInBytesLog2(lane_size); Simulator() local
9768 VectorFormat vform = SVEFormatFromLaneSizeInBytesLog2(lane_size); Simulator() local
9786 VectorFormat vform = instr->GetSVEVectorFormat(); Simulator() local
9867 VectorFormat vform = instr->GetSVEVectorFormat(); Simulator() local
9929 VectorFormat vform = SVEFormatFromLaneSizeInBytesLog2(lane_size); Simulator() local
9958 VectorFormat vform = instr->GetSVEVectorFormat(); Simulator() local
9989 VectorFormat vform = instr->GetSVEVectorFormat(); Simulator() local
10028 VectorFormat vform = instr->GetSVEVectorFormat(); Simulator() local
10102 VectorFormat vform = instr->GetSVEVectorFormat(); Simulator() local
10161 VectorFormat vform = instr->GetSVEVectorFormat(); Simulator() local
10170 VectorFormat vform = instr->GetSVEVectorFormat(); Simulator() local
10188 VectorFormat vform = instr->GetSVEVectorFormat(); Simulator() local
10245 VectorFormat vform = instr->GetSVEVectorFormat(); Simulator() local
10296 VectorFormat vform = instr->GetSVEVectorFormat(); Simulator() local
10313 VectorFormat vform = instr->GetSVEVectorFormat(); Simulator() local
10350 VectorFormat vform = instr->GetSVEVectorFormat(); Simulator() local
10390 VectorFormat vform = instr->GetSVEVectorFormat(); Simulator() local
10427 VectorFormat vform = instr->GetSVEVectorFormat(); Simulator() local
10452 VectorFormat vform = instr->GetSVEVectorFormat(); Simulator() local
10483 VectorFormat vform, vform_dup; Simulator() local
10515 VectorFormat vform = instr->GetSVEVectorFormat(); Simulator() local
10558 VectorFormat vform = kFormatUndefined; Simulator() local
10585 VectorFormat vform = instr->GetSVEVectorFormat(); Simulator() local
10654 VectorFormat vform = kFormatUndefined; Simulator() local
10738 VectorFormat vform = Simulator() local
10792 VectorFormat vform = instr->GetSVEVectorFormat(); Simulator() local
10813 VectorFormat vform = instr->GetSVEVectorFormat(); Simulator() local
10901 VectorFormat vform = Simulator() local
10912 VectorFormat vform = instr->GetSVEVectorFormat(); Simulator() local
10933 VectorFormat vform = instr->GetSVEVectorFormat(); Simulator() local
11049 VectorFormat vform = instr->GetSVEVectorFormat(); Simulator() local
11070 VectorFormat vform = instr->GetSVEVectorFormat(); Simulator() local
11101 VectorFormat vform = instr->GetSVEVectorFormat(); Simulator() local
11125 VectorFormat vform = instr->GetSVEVectorFormat(); Simulator() local
11152 VectorFormat vform = instr->GetSVEVectorFormat(); Simulator() local
11177 VectorFormat vform = instr->GetSVEVectorFormat(); Simulator() local
11210 VectorFormat vform = instr->GetSVEVectorFormat(); Simulator() local
11226 VectorFormat vform = instr->GetSVEVectorFormat(); Simulator() local
11255 VectorFormat vform = instr->GetSVEVectorFormat(); Simulator() local
11290 VectorFormat vform = instr->GetSVEVectorFormat(); Simulator() local
11405 VectorFormat vform = instr->GetSVEVectorFormat(); Simulator() local
11443 VectorFormat vform = instr->GetSVEVectorFormat(); Simulator() local
11528 VectorFormat vform = instr->GetSVEVectorFormat(); Simulator() local
11546 VectorFormat vform = instr->GetSVEVectorFormat(); Simulator() local
11580 VectorFormat vform = instr->GetSVEVectorFormat(); Simulator() local
11610 VectorFormat vform = instr->GetSVEVectorFormat(); Simulator() local
11632 VectorFormat vform = instr->GetSVEVectorFormat(); Simulator() local
11652 VectorFormat vform = instr->GetSVEVectorFormat(); Simulator() local
11700 VectorFormat vform = instr->GetSVEVectorFormat(); Simulator() local
11756 VectorFormat vform = instr->GetSVEVectorFormat(); Simulator() local
11780 VectorFormat vform = instr->GetSVEVectorFormat(); Simulator() local
11839 VectorFormat vform = instr->GetSVEVectorFormat(); Simulator() local
12057 VectorFormat vform = SVEFormatFromLaneSizeInBytesLog2(esize_in_bytes_log2); Simulator() local
12336 VectorFormat vform = SVEFormatFromLaneSizeInBytesLog2(esize_in_bytes_log2); Simulator() local
12380 VectorFormat vform = SVEFormatFromLaneSizeInBytesLog2(esize_in_bytes_log2); Simulator() local
12399 VectorFormat vform = kFormatUndefined; Simulator() local
12434 VectorFormat vform = kFormatUndefined; Simulator() local
12484 VectorFormat vform = SVEFormatFromLaneSizeInBytesLog2(msz); Simulator() local
12511 VectorFormat vform = SVEFormatFromLaneSizeInBytesLog2(msz); Simulator() local
12572 VectorFormat vform = SVEFormatFromLaneSizeInBytesLog2(msz); Simulator() local
12824 VectorFormat vform = kFormatUndefined; Simulator() local
12855 VectorFormat vform = kFormatUndefined; Simulator() local
12897 VectorFormat vform = Simulator() local
12923 VectorFormat vform = Simulator() local
12941 VectorFormat vform = instr->GetSVEVectorFormat(); Simulator() local
13008 VectorFormat vform = SVEFormatFromLaneSizeInBytesLog2(msz); Simulator() local
13068 VectorFormat vform = instr->GetSVEVectorFormat(); Simulator() local
13100 VectorFormat vform = kFormatVnS; Simulator() local
13134 VectorFormat vform = instr->GetSVEVectorFormat(); Simulator() local
13228 VectorFormat vform = instr->GetSVEVectorFormat(); Simulator() local
13265 VectorFormat vform = instr->GetSVEVectorFormat(); Simulator() local
13299 VectorFormat vform = instr->GetSVEVectorFormat(); Simulator() local
13331 VectorFormat vform = instr->GetSVEVectorFormat(); Simulator() local
13363 VectorFormat vform = instr->GetSVEVectorFormat(); Simulator() local
13392 VectorFormat vform = instr->GetSVEVectorFormat(); Simulator() local
13419 VectorFormat vform = instr->GetSVEVectorFormat(); Simulator() local
13447 VectorFormat vform = instr->GetSVEVectorFormat(); Simulator() local
13471 VectorFormat vform = instr->GetSVEVectorFormat(); Simulator() local
13488 VectorFormat vform = instr->GetSVEVectorFormat(); Simulator() local
13506 VectorFormat vform = instr->GetSVEVectorFormat(); Simulator() local
13586 VectorFormat vform = instr->GetSVEVectorFormat(); Simulator() local
13621 VectorFormat vform = instr->GetSVEVectorFormat(); Simulator() local
13634 VectorFormat vform = instr->GetSVEVectorFormat(); Simulator() local
13653 VectorFormat vform = Simulator() local
13671 VectorFormat vform = instr->GetSVEVectorFormat(); Simulator() local
13684 VectorFormat vform = instr->GetSVEVectorFormat(); Simulator() local
13705 VectorFormat vform = instr->GetSVEVectorFormat(); Simulator() local
13728 VectorFormat vform = instr->GetSVEVectorFormat(); Simulator() local
13808 VectorFormat vform = instr->GetSVEVectorFormat(); Simulator() local
13821 VectorFormat vform = instr->GetSVEVectorFormat(); Simulator() local
13957 VectorFormat vform = instr->GetSVEVectorFormat(); Simulator() local
14039 VectorFormat vform = SVEFormatFromLaneSizeInBytesLog2(esize_in_bytes_log2); Simulator() local
14083 VectorFormat vform = SVEFormatFromLaneSizeInBytesLog2(esize_in_bytes_log2); Simulator() local
[all...]
H A Dinstructions-aarch64.cc1006 VectorFormat VectorFormatHalfWidth(VectorFormat vform) { in VectorFormatHalfWidth() argument
1007 switch (vform) { in VectorFormatHalfWidth()
1033 VectorFormat VectorFormatDoubleWidth(VectorFormat vform) { in VectorFormatDoubleWidth() argument
1034 switch (vform) { in VectorFormatDoubleWidth()
1060 VectorFormat VectorFormatFillQ(VectorFormat vform) { in VectorFormatFillQ() argument
1061 switch (vform) { in VectorFormatFillQ()
1084 VectorFormat VectorFormatHalfWidthDoubleLanes(VectorFormat vform) { in VectorFormatHalfWidthDoubleLanes() argument
1085 switch (vform) { in VectorFormatHalfWidthDoubleLanes()
1110 VectorFormat VectorFormatDoubleLanes(VectorFormat vform) { in VectorFormatDoubleLanes() argument
1111 VIXL_ASSERT(vform in VectorFormatDoubleLanes()
1126 VectorFormatHalfLanes(VectorFormat vform) VectorFormatHalfLanes() argument
1159 IsSVEFormat(VectorFormat vform) IsSVEFormat() argument
1223 ScalarFormatFromFormat(VectorFormat vform) ScalarFormatFromFormat() argument
1228 RegisterSizeInBitsFromFormat(VectorFormat vform) RegisterSizeInBitsFromFormat() argument
1257 RegisterSizeInBytesFromFormat(VectorFormat vform) RegisterSizeInBytesFromFormat() argument
1262 LaneSizeInBitsFromFormat(VectorFormat vform) LaneSizeInBitsFromFormat() argument
1297 LaneSizeInBytesFromFormat(VectorFormat vform) LaneSizeInBytesFromFormat() argument
1302 LaneSizeInBytesLog2FromFormat(VectorFormat vform) LaneSizeInBytesLog2FromFormat() argument
1335 LaneCountFromFormat(VectorFormat vform) LaneCountFromFormat() argument
1363 MaxLaneCountFromFormat(VectorFormat vform) MaxLaneCountFromFormat() argument
1390 IsVectorFormat(VectorFormat vform) IsVectorFormat() argument
1404 MaxIntFromFormat(VectorFormat vform) MaxIntFromFormat() argument
1410 MinIntFromFormat(VectorFormat vform) MinIntFromFormat() argument
1415 MaxUintFromFormat(VectorFormat vform) MaxUintFromFormat() argument
[all...]
H A Dinstructions-aarch64.h771 VectorFormat VectorFormatHalfWidth(VectorFormat vform);
772 VectorFormat VectorFormatDoubleWidth(VectorFormat vform);
773 VectorFormat VectorFormatDoubleLanes(VectorFormat vform);
774 VectorFormat VectorFormatHalfLanes(VectorFormat vform);
776 VectorFormat VectorFormatHalfWidthDoubleLanes(VectorFormat vform);
777 VectorFormat VectorFormatFillQ(VectorFormat vform);
778 VectorFormat ScalarFormatFromFormat(VectorFormat vform);
782 unsigned RegisterSizeInBitsFromFormat(VectorFormat vform);
783 unsigned RegisterSizeInBytesFromFormat(VectorFormat vform);
784 bool IsSVEFormat(VectorFormat vform);
912 static const VectorFormat vform[] = {kFormatUndefined, GetVectorFormat() local
[all...]
H A Ddisasm-aarch64.cc2589 VectorFormat vform = nfd.GetVectorFormat(); in Disassembler() local
2590 if ((vform == kFormatD) || in Disassembler()
2591 ((vform == kFormatS) && (instr->ExtractBit(30) == 0))) { in Disassembler()
3294 VectorFormat vform = nfd.GetVectorFormat(0); in Disassembler() local
3300 if (vform != kFormatD) { in Disassembler()
3306 if ((vform == kFormatB) || (vform == kFormatD)) { in Disassembler()
5377 VectorFormat vform = instr->GetSVEVectorFormat(); in Disassembler() local
5382 if (vform == kFormatVnS) { in Disassembler()
5389 if (vform in Disassembler()
5596 VectorFormat vform = instr->GetSVEVectorFormat(); Disassembler() local
5699 VectorFormat vform = instr->GetSVEVectorFormat(); Disassembler() local
5893 VectorFormat vform = instr->GetSVEVectorFormat(); Disassembler() local
[all...]
/third_party/node/deps/v8/src/execution/arm64/
H A Dsimulator-logic-arm64.cc346 void Simulator::ld1(VectorFormat vform, LogicVRegister dst, uint64_t addr) { in ld1() argument
347 dst.ClearForWrite(vform); in ld1()
348 for (int i = 0; i < LaneCountFromFormat(vform); i++) { in ld1()
349 dst.ReadUintFromMem(vform, i, addr); in ld1()
350 addr += LaneSizeInBytesFromFormat(vform); in ld1()
354 void Simulator::ld1(VectorFormat vform, LogicVRegister dst, int index, in ld1() argument
356 dst.ReadUintFromMem(vform, index, addr); in ld1()
359 void Simulator::ld1r(VectorFormat vform, LogicVRegister dst, uint64_t addr) { in ld1r() argument
360 dst.ClearForWrite(vform); in ld1r()
361 for (int i = 0; i < LaneCountFromFormat(vform); in ld1r()
366 ld2(VectorFormat vform, LogicVRegister dst1, LogicVRegister dst2, uint64_t addr1) ld2() argument
380 ld2(VectorFormat vform, LogicVRegister dst1, LogicVRegister dst2, int index, uint64_t addr1) ld2() argument
389 ld2r(VectorFormat vform, LogicVRegister dst1, LogicVRegister dst2, uint64_t addr) ld2r() argument
400 ld3(VectorFormat vform, LogicVRegister dst1, LogicVRegister dst2, LogicVRegister dst3, uint64_t addr1) ld3() argument
418 ld3(VectorFormat vform, LogicVRegister dst1, LogicVRegister dst2, LogicVRegister dst3, int index, uint64_t addr1) ld3() argument
431 ld3r(VectorFormat vform, LogicVRegister dst1, LogicVRegister dst2, LogicVRegister dst3, uint64_t addr) ld3r() argument
445 ld4(VectorFormat vform, LogicVRegister dst1, LogicVRegister dst2, LogicVRegister dst3, LogicVRegister dst4, uint64_t addr1) ld4() argument
468 ld4(VectorFormat vform, LogicVRegister dst1, LogicVRegister dst2, LogicVRegister dst3, LogicVRegister dst4, int index, uint64_t addr1) ld4() argument
484 ld4r(VectorFormat vform, LogicVRegister dst1, LogicVRegister dst2, LogicVRegister dst3, LogicVRegister dst4, uint64_t addr) ld4r() argument
502 st1(VectorFormat vform, LogicVRegister src, uint64_t addr) st1() argument
509 st1(VectorFormat vform, LogicVRegister src, int index, uint64_t addr) st1() argument
514 st2(VectorFormat vform, LogicVRegister dst, LogicVRegister dst2, uint64_t addr) st2() argument
526 st2(VectorFormat vform, LogicVRegister dst, LogicVRegister dst2, int index, uint64_t addr) st2() argument
533 st3(VectorFormat vform, LogicVRegister dst, LogicVRegister dst2, LogicVRegister dst3, uint64_t addr) st3() argument
548 st3(VectorFormat vform, LogicVRegister dst, LogicVRegister dst2, LogicVRegister dst3, int index, uint64_t addr) st3() argument
556 st4(VectorFormat vform, LogicVRegister dst, LogicVRegister dst2, LogicVRegister dst3, LogicVRegister dst4, uint64_t addr) st4() argument
574 st4(VectorFormat vform, LogicVRegister dst, LogicVRegister dst2, LogicVRegister dst3, LogicVRegister dst4, int index, uint64_t addr) st4() argument
584 cmp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, Condition cond) cmp() argument
624 cmp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, int imm, Condition cond) cmp() argument
632 cmptst(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) cmptst() argument
644 add(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) add() argument
673 addp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) addp() argument
683 mla(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) mla() argument
692 mls(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) mls() argument
701 mul(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) mul() argument
711 mul(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) mul() argument
719 mla(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) mla() argument
727 mls(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) mls() argument
735 smull(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) smull() argument
744 smull2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) smull2() argument
753 umull(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) umull() argument
762 umull2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) umull2() argument
771 smlal(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) smlal() argument
780 smlal2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) smlal2() argument
789 umlal(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) umlal() argument
798 umlal2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) umlal2() argument
807 smlsl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) smlsl() argument
816 smlsl2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) smlsl2() argument
825 umlsl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) umlsl() argument
834 umlsl2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) umlsl2() argument
843 sqdmull(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) sqdmull() argument
852 sqdmull2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) sqdmull2() argument
861 sqdmlal(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) sqdmlal() argument
870 sqdmlal2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) sqdmlal2() argument
879 sqdmlsl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) sqdmlsl() argument
888 sqdmlsl2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) sqdmlsl2() argument
897 sqdmulh(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) sqdmulh() argument
905 sqrdmulh(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) sqrdmulh() argument
924 pmul(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) pmul() argument
935 pmull(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) pmull() argument
948 pmull2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) pmull2() argument
962 sub(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) sub() argument
991 and_(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) and_() argument
1001 orr(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) orr() argument
1011 orn(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) orn() argument
1021 eor(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) eor() argument
1031 bic(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) bic() argument
1041 bic(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, uint64_t imm) bic() argument
1052 bif(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) bif() argument
1066 bit(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) bit() argument
1080 bsl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) bsl() argument
1094 SMinMax(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, bool max) SMinMax() argument
1112 smax(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) smax() argument
1118 smin(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) smin() argument
1124 SMinMaxP(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, bool max) SMinMaxP() argument
1149 smaxp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) smaxp() argument
1155 sminp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) sminp() argument
1161 addp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) addp() argument
1171 addv(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) addv() argument
1186 saddlv(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) saddlv() argument
1201 uaddlv(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) uaddlv() argument
1216 SMinMaxV(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, bool max) SMinMaxV() argument
1232 smaxv(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) smaxv() argument
1238 sminv(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) sminv() argument
1244 UMinMax(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, bool max) UMinMax() argument
1262 umax(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) umax() argument
1268 umin(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) umin() argument
1274 UMinMaxP(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, bool max) UMinMaxP() argument
1299 umaxp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) umaxp() argument
1305 uminp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) uminp() argument
1311 UMinMaxV(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, bool max) UMinMaxV() argument
1327 umaxv(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) umaxv() argument
1333 uminv(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) uminv() argument
1339 shl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int shift) shl() argument
1347 sshll(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int shift) sshll() argument
1356 sshll2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int shift) sshll2() argument
1365 shll(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) shll() argument
1371 shll2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) shll2() argument
1377 ushll(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int shift) ushll() argument
1386 ushll2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int shift) ushll2() argument
1395 sli(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int shift) sli() argument
1409 sqshl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int shift) sqshl() argument
1417 uqshl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int shift) uqshl() argument
1425 sqshlu(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int shift) sqshlu() argument
1433 sri(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int shift) sri() argument
1456 ushr(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int shift) ushr() argument
1464 sshr(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int shift) sshr() argument
1472 ssra(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int shift) ssra() argument
1479 usra(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int shift) usra() argument
1486 srsra(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int shift) srsra() argument
1493 ursra(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int shift) ursra() argument
1500 cls(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) cls() argument
1513 clz(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) clz() argument
1526 cnt(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) cnt() argument
1544 sshl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) sshl() argument
1603 ushl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) ushl() argument
1640 neg(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) neg() argument
1654 suqadd(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) suqadd() argument
1672 usqadd(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) usqadd() argument
1691 abs(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) abs() argument
1809 xtn(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) xtn() argument
1814 sqxtn(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) sqxtn() argument
1819 sqxtun(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) sqxtun() argument
1824 uqxtn(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) uqxtn() argument
1829 AbsDiff(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, bool issigned) AbsDiff() argument
1847 saba(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) saba() argument
1857 uaba(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) uaba() argument
1867 not_(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) not_() argument
1876 rbit(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) rbit() argument
1897 rev(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int revSize) rev() argument
1912 rev16(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) rev16() argument
1917 rev32(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) rev32() argument
1922 rev64(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) rev64() argument
1927 addlp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, bool is_signed, bool do_accumulate) addlp() argument
1956 saddlp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) saddlp() argument
1961 uaddlp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) uaddlp() argument
1966 sadalp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) sadalp() argument
1971 uadalp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) uadalp() argument
1976 ext(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) ext() argument
1994 dup_element(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int src_index) dup_element() argument
2006 dup_immediate(VectorFormat vform, LogicVRegister dst, uint64_t imm) dup_immediate() argument
2017 ins_element(VectorFormat vform, LogicVRegister dst, int dst_index, const LogicVRegister& src, int src_index) ins_element() argument
2024 ins_immediate(VectorFormat vform, LogicVRegister dst, int dst_index, uint64_t imm) ins_immediate() argument
2031 movi(VectorFormat vform, LogicVRegister dst, uint64_t imm) movi() argument
2041 mvni(VectorFormat vform, LogicVRegister dst, uint64_t imm) mvni() argument
2051 orr(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, uint64_t imm) orr() argument
2062 uxtl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) uxtl() argument
2073 sxtl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) sxtl() argument
2084 uxtl2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) uxtl2() argument
2096 sxtl2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) sxtl2() argument
2108 shrn(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int shift) shrn() argument
2117 shrn2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int shift) shrn2() argument
2126 rshrn(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int shift) rshrn() argument
2135 rshrn2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int shift) rshrn2() argument
2144 Table(VectorFormat vform, LogicVRegister dst, const LogicVRegister& ind, bool zero_out_of_bounds, const LogicVRegister* tab1, const LogicVRegister* tab2, const LogicVRegister* tab3, const LogicVRegister* tab4) Table() argument
2169 tbl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& tab, const LogicVRegister& ind) tbl() argument
2175 tbl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& tab, const LogicVRegister& tab2, const LogicVRegister& ind) tbl() argument
2182 tbl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& tab, const LogicVRegister& tab2, const LogicVRegister& tab3, const LogicVRegister& ind) tbl() argument
2190 tbl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& tab, const LogicVRegister& tab2, const LogicVRegister& tab3, const LogicVRegister& tab4, const LogicVRegister& ind) tbl() argument
2199 tbx(VectorFormat vform, LogicVRegister dst, const LogicVRegister& tab, const LogicVRegister& ind) tbx() argument
2205 tbx(VectorFormat vform, LogicVRegister dst, const LogicVRegister& tab, const LogicVRegister& tab2, const LogicVRegister& ind) tbx() argument
2212 tbx(VectorFormat vform, LogicVRegister dst, const LogicVRegister& tab, const LogicVRegister& tab2, const LogicVRegister& tab3, const LogicVRegister& ind) tbx() argument
2220 tbx(VectorFormat vform, LogicVRegister dst, const LogicVRegister& tab, const LogicVRegister& tab2, const LogicVRegister& tab3, const LogicVRegister& tab4, const LogicVRegister& ind) tbx() argument
2229 uqshrn(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int shift) uqshrn() argument
2234 uqshrn2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int shift) uqshrn2() argument
2239 uqrshrn(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int shift) uqrshrn() argument
2244 uqrshrn2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int shift) uqrshrn2() argument
2249 sqshrn(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int shift) sqshrn() argument
2258 sqshrn2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int shift) sqshrn2() argument
2267 sqrshrn(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int shift) sqrshrn() argument
2276 sqrshrn2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int shift) sqrshrn2() argument
2285 sqshrun(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int shift) sqshrun() argument
2294 sqshrun2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int shift) sqshrun2() argument
2303 sqrshrun(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int shift) sqrshrun() argument
2312 sqrshrun2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int shift) sqrshrun2() argument
2321 uaddl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) uaddl() argument
2331 uaddl2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) uaddl2() argument
2341 uaddw(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) uaddw() argument
2350 uaddw2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) uaddw2() argument
2359 saddl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) saddl() argument
2369 saddl2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) saddl2() argument
2379 saddw(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) saddw() argument
2388 saddw2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) saddw2() argument
2397 usubl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) usubl() argument
2407 usubl2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) usubl2() argument
2417 usubw(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) usubw() argument
2426 usubw2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) usubw2() argument
2435 ssubl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) ssubl() argument
2445 ssubl2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) ssubl2() argument
2455 ssubw(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) ssubw() argument
2464 ssubw2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) ssubw2() argument
2473 uabal(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) uabal() argument
2483 uabal2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) uabal2() argument
2493 sabal(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) sabal() argument
2503 sabal2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) sabal2() argument
2513 uabdl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) uabdl() argument
2523 uabdl2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) uabdl2() argument
2533 sabdl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) sabdl() argument
2543 sabdl2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) sabdl2() argument
2553 umull(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) umull() argument
2563 umull2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) umull2() argument
2573 smull(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) smull() argument
2583 smull2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) smull2() argument
2593 umlsl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) umlsl() argument
2603 umlsl2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) umlsl2() argument
2613 smlsl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) smlsl() argument
2623 smlsl2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) smlsl2() argument
2633 umlal(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) umlal() argument
2643 umlal2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) umlal2() argument
2653 smlal(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) smlal() argument
2663 smlal2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) smlal2() argument
2673 sqdmlal(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) sqdmlal() argument
2681 sqdmlal2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) sqdmlal2() argument
2689 sqdmlsl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) sqdmlsl() argument
2697 sqdmlsl2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) sqdmlsl2() argument
2705 sqdmull(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) sqdmull() argument
2713 sqdmull2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) sqdmull2() argument
2721 sqrdmulh(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, bool round) sqrdmulh() argument
2748 sqdmulh(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) sqdmulh() argument
2754 addhn(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) addhn() argument
2763 addhn2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) addhn2() argument
2772 raddhn(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) raddhn() argument
2781 raddhn2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) raddhn2() argument
2790 subhn(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) subhn() argument
2799 subhn2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) subhn2() argument
2808 rsubhn(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) rsubhn() argument
2817 rsubhn2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) rsubhn2() argument
2826 trn1(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) trn1() argument
2841 trn2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) trn2() argument
2856 zip1(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) zip1() argument
2871 zip2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) zip2() argument
2886 uzp1(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) uzp1() argument
2903 uzp2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) uzp2() argument
3277 fnmul(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) fnmul() argument
3286 frecps(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) frecps() argument
3299 frecps(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) frecps() argument
3312 frsqrts(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) frsqrts() argument
3384 frsqrts(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) frsqrts() argument
3397 fcmp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, Condition cond) fcmp() argument
3432 fcmp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, Condition cond) fcmp() argument
3444 fcmp_zero(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, Condition cond) fcmp_zero() argument
3460 fabscmp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, Condition cond) fabscmp() argument
3478 fmla(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) fmla() argument
3492 fmla(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) fmla() argument
3505 fmls(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) fmls() argument
3519 fmls(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) fmls() argument
3532 fneg(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) fneg() argument
3543 fneg(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) fneg() argument
3555 fabs_(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) fabs_() argument
3568 fabs_(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) fabs_() argument
3579 fabd(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) fabd() argument
3588 fsqrt(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) fsqrt() argument
3633 FMinMaxV(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, FPMinMaxOp Op) FMinMaxV() argument
3645 fmaxv(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) fmaxv() argument
3650 fminv(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) fminv() argument
3655 fmaxnmv(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) fmaxnmv() argument
3660 fminnmv(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) fminnmv() argument
3665 fmul(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) fmul() argument
3681 fmla(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) fmla() argument
3697 fmls(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) fmls() argument
3713 fmulx(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) fmulx() argument
3730 frint(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, FPRounding rounding_mode, bool inexact_exception) frint() argument
3758 fcvts(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, FPRounding rounding_mode, int fbits) fcvts() argument
3777 fcvtu(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, FPRounding rounding_mode, int fbits) fcvtu() argument
3796 fcvtl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) fcvtl() argument
3811 fcvtl2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) fcvtl2() argument
3827 fcvtn(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) fcvtn() argument
3843 fcvtn2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) fcvtn2() argument
3859 fcvtxn(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) fcvtxn() argument
3869 fcvtxn2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) fcvtxn2() argument
3966 frsqrte(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) frsqrte() argument
4087 frecpe(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, FPRounding round) frecpe() argument
4105 ursqrte(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) ursqrte() argument
4135 urecpe(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) urecpe() argument
4156 frecpx(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) frecpx() argument
4184 frecpx(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src) frecpx() argument
4195 scvtf(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int fbits, FPRounding round) scvtf() argument
4211 ucvtf(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int fbits, FPRounding round) ucvtf() argument
[all...]
H A Dsimulator-arm64.h390 int64_t Int(VectorFormat vform, int index) const { in Int() argument
392 switch (LaneSizeInBitsFromFormat(vform)) { in Int()
412 uint64_t Uint(VectorFormat vform, int index) const { in Uint() argument
414 switch (LaneSizeInBitsFromFormat(vform)) { in Uint()
434 uint64_t UintLeftJustified(VectorFormat vform, int index) const { in UintLeftJustified() argument
435 return Uint(vform, index) << (64 - LaneSizeInBitsFromFormat(vform)); in UintLeftJustified()
438 int64_t IntLeftJustified(VectorFormat vform, int index) const { in IntLeftJustified() argument
439 uint64_t value = UintLeftJustified(vform, index); in IntLeftJustified()
445 void SetInt(VectorFormat vform, in argument
465 SetIntArray(VectorFormat vform, const int64_t* src) const SetIntArray() argument
472 SetUint(VectorFormat vform, int index, uint64_t value) const SetUint() argument
492 SetUintArray(VectorFormat vform, const uint64_t* src) const SetUintArray() argument
562 SignedSaturate(VectorFormat vform) SignedSaturate() argument
574 UnsignedSaturate(VectorFormat vform) UnsignedSaturate() argument
593 Round(VectorFormat vform) Round() argument
602 Uhalve(VectorFormat vform) Uhalve() argument
618 Halve(VectorFormat vform) Halve() argument
[all...]
H A Dsimulator-arm64.cc982 void LogicVRegister::ReadUintFromMem(VectorFormat vform, int index, in ReadUintFromMem() argument
984 switch (LaneSizeInBitsFromFormat(vform)) { in ReadUintFromMem()
1002 void LogicVRegister::WriteUintToMem(VectorFormat vform, int index, in WriteUintToMem() argument
1004 switch (LaneSizeInBitsFromFormat(vform)) { in WriteUintToMem()
1006 SimMemory::Write<uint8_t>(addr, static_cast<uint8_t>(Uint(vform, index))); in WriteUintToMem()
1010 static_cast<uint16_t>(Uint(vform, index))); in WriteUintToMem()
1014 static_cast<uint32_t>(Uint(vform, index))); in WriteUintToMem()
1017 SimMemory::Write<uint64_t>(addr, Uint(vform, index)); in WriteUintToMem()
1245 VectorFormat vform) {
1246 switch (vform) {
[all...]

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