| /third_party/ffmpeg/libavcodec/arm/ |
| H A D | vp6dsp_neon.S | 47 vcge.u16 q12, q12, q8 @ V-t-1 >= t-1
48 vcge.u16 d31, d31, d16
|
| /third_party/node/deps/v8/src/diagnostics/arm/ |
| H A D | disasm-arm.cc | 2058 Format(instr, "vcge.s'size3 'Qd, 'Qn, 'Qm"); in DecodeAdvancedSIMDDataProcessing()
2108 Format(instr, "vcge.u'size3 'Qd, 'Qn, 'Qm"); in DecodeAdvancedSIMDDataProcessing()
2130 Format(instr, "vcge.f32 'Qd, 'Qn, 'Qm"); in DecodeAdvancedSIMDDataProcessing()
|
| /third_party/vixl/test/aarch32/ |
| H A D | test-assembler-cond-dt-drt-drd-drn-drm-float-f32-only-a32.cc | 55 M(vcge) \
211 #include "aarch32/traces/assembler-cond-dt-drt-drd-drn-drm-float-f32-only-vcge-a32.h"
|
| H A D | test-assembler-cond-dt-drt-drd-drn-drm-float-f32-only-t32.cc | 55 M(vcge) \
211 #include "aarch32/traces/assembler-cond-dt-drt-drd-drn-drm-float-f32-only-vcge-t32.h"
|
| /third_party/node/deps/v8/src/compiler/backend/arm/ |
| H A D | code-generator-arm.cc | 2274 __ vcge(i.OutputSimd128Register(), i.InputSimd128Register(1), in AssembleArchInstruction()
2416 __ vcge(NeonS32, i.OutputSimd128Register(), i.InputSimd128Register(0), in AssembleArchInstruction()
2454 __ vcge(NeonU32, i.OutputSimd128Register(), i.InputSimd128Register(0), in AssembleArchInstruction()
2606 __ vcge(NeonS16, i.OutputSimd128Register(), i.InputSimd128Register(0), in AssembleArchInstruction()
2653 __ vcge(NeonU16, i.OutputSimd128Register(), i.InputSimd128Register(0), in AssembleArchInstruction()
2771 __ vcge(NeonS8, i.OutputSimd128Register(), i.InputSimd128Register(0), in AssembleArchInstruction()
2808 __ vcge(NeonU8, i.OutputSimd128Register(), i.InputSimd128Register(0), in AssembleArchInstruction()
|
| /third_party/vixl/src/aarch32/ |
| H A D | assembler-aarch32.h | 4064 void vcge(Condition cond,
4069 void vcge(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) { in vcge() function in vixl::aarch32::Assembler
4070 vcge(al, dt, rd, rm, operand); in vcge()
4073 void vcge(Condition cond,
4078 void vcge(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) { in vcge() function in vixl::aarch32::Assembler
4079 vcge(al, dt, rd, rm, operand); in vcge()
4082 void vcge(
4084 void vcge(DataType dt, DRegister rd, DRegister rn, DRegister rm) { in vcge() function in vixl::aarch32::Assembler
4085 vcge(al, dt, rd, rn, rm); in vcge()
4088 void vcge(
4090 void vcge(DataType dt, QRegister rd, QRegister rn, QRegister rm) { vcge() function in vixl::aarch32::Assembler
[all...] |
| H A D | disasm-aarch32.h | 1590 void vcge(Condition cond,
1596 void vcge(Condition cond,
1602 void vcge(
1605 void vcge(
|
| H A D | disasm-aarch32.cc | 4119 void Disassembler::vcge(Condition cond, in vcge() function in vixl::aarch32::Disassembler
4133 void Disassembler::vcge(Condition cond, in vcge() function in vixl::aarch32::Disassembler
4147 void Disassembler::vcge( in vcge() function in vixl::aarch32::Disassembler
4158 void Disassembler::vcge( in vcge() function in vixl::aarch32::Disassembler
[all...] |
| H A D | assembler-aarch32.cc | 15203 void Assembler::vcge(Condition cond, in vcge() function in vixl::aarch32::Assembler
15240 Delegate(kVcge, &Assembler::vcge, cond, dt, rd, rm, operand); in vcge()
15243 void Assembler::vcge(Condition cond, in vcge() function in vixl::aarch32::Assembler
15280 Delegate(kVcge, &Assembler::vcge, cond, dt, rd, rm, operand); in vcge()
15283 void Assembler::vcge( in vcge() function in vixl::aarch32::Assembler
15327 Delegate(kVcge, &Assembler::vcge, cond, dt, rd, rn, rm); in vcge()
15330 void Assembler::vcge( in vcge() function in vixl::aarch32::Assembler
15374 Delegate(kVcge, &Assembler::vcge, cond, dt, rd, rn, rm); in vcge()
|
| H A D | macro-assembler-aarch32.h | 7168 vcge(cond, dt, rd, rm, operand); in MacroAssembler()
7190 vcge(cond, dt, rd, rm, operand); in MacroAssembler()
7209 vcge(cond, dt, rd, rn, rm); in MacroAssembler()
7228 vcge(cond, dt, rd, rn, rm); in MacroAssembler()
|
| /third_party/node/deps/v8/src/codegen/arm/ |
| H A D | assembler-arm.h | 961 void vcge(QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2);
962 void vcge(NeonDataType dt, QwNeonRegister dst, QwNeonRegister src1,
|
| H A D | assembler-arm.cc | 4902 void Assembler::vcge(QwNeonRegister dst, QwNeonRegister src1, in vcge() function in v8::internal::Assembler
4905 // Qd = vcge(Qn, Qm) SIMD floating point compare greater or equal. in vcge()
4910 void Assembler::vcge(NeonDataType dt, QwNeonRegister dst, QwNeonRegister src1, in vcge() function in v8::internal::Assembler
4913 // Qd = vcge(Qn, Qm) SIMD integer compare greater or equal. in vcge()
|
| /third_party/node/deps/v8/src/wasm/baseline/arm/ |
| H A D | liftoff-assembler-arm.h | 3710 vcge(NeonS8, liftoff::GetSimd128Register(dst),
3716 vcge(NeonU8, liftoff::GetSimd128Register(dst),
3747 vcge(NeonS16, liftoff::GetSimd128Register(dst),
3753 vcge(NeonU16, liftoff::GetSimd128Register(dst),
3784 vcge(NeonS32, liftoff::GetSimd128Register(dst),
3790 vcge(NeonU32, liftoff::GetSimd128Register(dst),
3839 vcge(liftoff::GetSimd128Register(dst), liftoff::GetSimd128Register(rhs),
|