Home
last modified time | relevance | path

Searched refs:vceq (Results 1 - 21 of 21) sorted by relevance

/third_party/ffmpeg/libavcodec/arm/
H A Dmpegvideo_neon.S46 vceq.s16 q1, q0, #0
53 vceq.s16 q9, q8, #0
67 vceq.s16 d1, d0, #0
H A Dsbrdsp_neon.S321 vceq.f32 d16, d2, #0
340 vceq.f32 d4, d2, #0
369 vceq.f32 d16, d2, #0
388 vceq.f32 d4, d2, #0
H A Drv40dsp_neon.S824 vceq.i16 d16, d19, #0 @ !t
/third_party/node/deps/openssl/openssl/crypto/perlasm/
H A Ds390x.pm55 vech vecf vecg vecl veclb veclh veclf veclg vceq vceqb vceqh vceqf
847 sub vceq { subroutine
852 vceq(@_,0,0);
855 vceq(@_,1,0);
858 vceq(@_,2,0);
861 vceq(@_,3,0);
864 vceq(@_,0,1);
867 vceq(@_,1,1);
870 vceq(@_,2,1);
873 vceq(
[all...]
/third_party/openssl/crypto/perlasm/
H A Ds390x.pm55 vech vecf vecg vecl veclb veclh veclf veclg vceq vceqb vceqh vceqf
847 sub vceq { subroutine
852 vceq(@_,0,0);
855 vceq(@_,1,0);
858 vceq(@_,2,0);
861 vceq(@_,3,0);
864 vceq(@_,0,1);
867 vceq(@_,1,1);
870 vceq(@_,2,1);
873 vceq(
[all...]
/third_party/node/deps/v8/src/diagnostics/arm/
H A Ddisasm-arm.cc2086 Format(instr, "vceq.f32 'Qd, 'Qn, 'Qm"); in DecodeAdvancedSIMDDataProcessing()
2118 Format(instr, "vceq.i'size3 'Qd, 'Qn, 'Qm"); in DecodeAdvancedSIMDDataProcessing()
2284 q ? "vceq.s'size2 'Qd, 'Qm, #0" : "vceq.s.'size2 'Dd, 'Dm, #0"); in DecodeAdvancedSIMDTwoOrThreeRegisters()
/third_party/node/deps/v8/src/codegen/s390/
H A Dmacro-assembler-s390.cc5250 vceq(dst, src, src, Condition(0), Condition(3)); in CallRecordWriteStub()
5304 V(I64x2Eq, vceq, 0, 3) \ in CallRecordWriteStub()
5306 V(I32x4Eq, vceq, 0, 2) \ in CallRecordWriteStub()
5309 V(I16x8Eq, vceq, 0, 1) \ in CallRecordWriteStub()
5312 V(I8x16Eq, vceq, 0, 0) \ in CallRecordWriteStub()
5452 vceq(scratch2, src, scratch2, Condition(0), Condition(mode)); \ in CallRecordWriteStub()
5524 vceq(dst, src1, src2, Condition(0), Condition(3)); in CallRecordWriteStub()
5537 vceq(dst, src1, src2, Condition(0), Condition(2)); in CallRecordWriteStub()
5550 vceq(scratch, src1, src2, Condition(0), Condition(2)); in CallRecordWriteStub()
5557 vceq(ds in CallRecordWriteStub()
[all...]
H A Dconstants-s390.h505 V(vceq, VCEQ, 0xE7F8) /* type = VRR_B VECTOR COMPARE EQUAL */ \
/third_party/vixl/test/aarch32/
H A Dtest-assembler-cond-dt-drt-drd-drn-drm-float-f32-only-a32.cc52 M(vceq) \
210 #include "aarch32/traces/assembler-cond-dt-drt-drd-drn-drm-float-f32-only-vceq-a32.h"
H A Dtest-assembler-cond-dt-drt-drd-drn-drm-float-f32-only-t32.cc52 M(vceq) \
210 #include "aarch32/traces/assembler-cond-dt-drt-drd-drn-drm-float-f32-only-vceq-t32.h"
/third_party/node/deps/v8/src/compiler/backend/arm/
H A Dcode-generator-arm.cc2258 __ vceq(i.OutputSimd128Register(), i.InputSimd128Register(0), in AssembleArchInstruction()
2264 __ vceq(dst, i.InputSimd128Register(0), i.InputSimd128Register(1)); in AssembleArchInstruction()
2399 __ vceq(Neon32, i.OutputSimd128Register(), i.InputSimd128Register(0), in AssembleArchInstruction()
2405 __ vceq(Neon32, dst, i.InputSimd128Register(0), in AssembleArchInstruction()
2589 __ vceq(Neon16, i.OutputSimd128Register(), i.InputSimd128Register(0), in AssembleArchInstruction()
2595 __ vceq(Neon16, dst, i.InputSimd128Register(0), in AssembleArchInstruction()
2755 __ vceq(Neon8, i.OutputSimd128Register(), i.InputSimd128Register(0), in AssembleArchInstruction()
2761 __ vceq(Neon8, dst, i.InputSimd128Register(0), i.InputSimd128Register(1)); in AssembleArchInstruction()
/third_party/node/deps/v8/src/codegen/arm/
H A Dassembler-arm.h957 void vceq(QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2);
958 void vceq(NeonSize size, QwNeonRegister dst, QwNeonRegister src1,
960 void vceq(NeonSize size, QwNeonRegister dst, QwNeonRegister src, int value);
H A Dmacro-assembler-arm.cc2676 vceq(Neon32, dst, src1, src2); in CallRecordWriteStub()
2685 vceq(Neon32, dst, src1, src2); in CallRecordWriteStub()
2714 vceq(Neon32, tmp, tmp, 0); in CallRecordWriteStub()
H A Dassembler-arm.cc4877 void Assembler::vceq(QwNeonRegister dst, QwNeonRegister src1, in vceq() function in v8::internal::Assembler
4880 // Qd = vceq(Qn, Qm) SIMD floating point compare equal. in vceq()
4885 void Assembler::vceq(NeonSize size, QwNeonRegister dst, QwNeonRegister src1, in vceq() function in v8::internal::Assembler
4888 // Qd = vceq(Qn, Qm) SIMD integer compare equal. in vceq()
4893 void Assembler::vceq(NeonSize size, QwNeonRegister dst, QwNeonRegister src1, in vceq() function in v8::internal::Assembler
4897 // Qd = vceq(Qn, Qm, #0) Vector Compare Equal to Zero. in vceq()
/third_party/vixl/src/aarch32/
H A Dassembler-aarch32.h4034 void vceq(Condition cond,
4039 void vceq(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) { in vceq() function in vixl::aarch32::Assembler
4040 vceq(al, dt, rd, rm, operand); in vceq()
4043 void vceq(Condition cond,
4048 void vceq(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) { in vceq() function in vixl::aarch32::Assembler
4049 vceq(al, dt, rd, rm, operand); in vceq()
4052 void vceq(
4054 void vceq(DataType dt, DRegister rd, DRegister rn, DRegister rm) { in vceq() function in vixl::aarch32::Assembler
4055 vceq(al, dt, rd, rn, rm); in vceq()
4058 void vceq(
4060 void vceq(DataType dt, QRegister rd, QRegister rn, QRegister rm) { vceq() function in vixl::aarch32::Assembler
[all...]
H A Ddisasm-aarch32.h1572 void vceq(Condition cond,
1578 void vceq(Condition cond,
1584 void vceq(
1587 void vceq(
H A Ddisasm-aarch32.cc4069 void Disassembler::vceq(Condition cond, in vceq() function in vixl::aarch32::Disassembler
4083 void Disassembler::vceq(Condition cond, in vceq() function in vixl::aarch32::Disassembler
4097 void Disassembler::vceq( in vceq() function in vixl::aarch32::Disassembler
4108 void Disassembler::vceq( in vceq() function in vixl::aarch32::Disassembler
[all...]
H A Dassembler-aarch32.cc15031 void Assembler::vceq(Condition cond, in vceq() function in vixl::aarch32::Assembler
15068 Delegate(kVceq, &Assembler::vceq, cond, dt, rd, rm, operand); in vceq()
15071 void Assembler::vceq(Condition cond, in vceq() function in vixl::aarch32::Assembler
15108 Delegate(kVceq, &Assembler::vceq, cond, dt, rd, rm, operand); in vceq()
15111 void Assembler::vceq( in vceq() function in vixl::aarch32::Assembler
15154 Delegate(kVceq, &Assembler::vceq, cond, dt, rd, rn, rm); in vceq()
15157 void Assembler::vceq( in vceq() function in vixl::aarch32::Assembler
15200 Delegate(kVceq, &Assembler::vceq, cond, dt, rd, rn, rm); in vceq()
H A Dmacro-assembler-aarch32.h7086 vceq(cond, dt, rd, rm, operand); in MacroAssembler()
7108 vceq(cond, dt, rd, rm, operand); in MacroAssembler()
7127 vceq(cond, dt, rd, rn, rm); in MacroAssembler()
7146 vceq(cond, dt, rd, rn, rm); in MacroAssembler()
/third_party/node/deps/v8/src/wasm/baseline/arm/
H A Dliftoff-assembler-arm.h3685 vceq(Neon8, liftoff::GetSimd128Register(dst),
3691 vceq(Neon8, liftoff::GetSimd128Register(dst),
3722 vceq(Neon16, liftoff::GetSimd128Register(dst),
3728 vceq(Neon16, liftoff::GetSimd128Register(dst),
3759 vceq(Neon32, liftoff::GetSimd128Register(dst),
3765 vceq(Neon32, liftoff::GetSimd128Register(dst),
3820 vceq(liftoff::GetSimd128Register(dst), liftoff::GetSimd128Register(lhs),
3826 vceq(liftoff::GetSimd128Register(dst), liftoff::GetSimd128Register(lhs),
/third_party/node/deps/v8/src/execution/s390/
H A Dsimulator-s390.cc797 V(vceq, VCEQ, 0xE7F8) /* type = VRR_B VECTOR COMPARE EQUAL */ \ in EvalTableInit()

Completed in 187 milliseconds