| /third_party/mesa3d/src/gallium/drivers/radeonsi/ |
| H A D | si_shader_llvm_vs.c | 422 args->valid_mask = 0; in si_llvm_clipvertex_to_clipdist()
434 args->valid_mask = 0; /* Specify whether the EXEC mask represents the valid mask */ in si_llvm_init_vs_export_args()
563 pos_args[0].valid_mask = 0; /* EXEC mask */ in si_llvm_build_vs_exports()
584 pos_args[1].valid_mask = 0; /* EXEC mask */ in si_llvm_build_vs_exports()
675 * Setting valid_mask=1 prevents it and has no other effect. in si_llvm_build_vs_exports()
678 pos_args[0].valid_mask = 1; in si_llvm_build_vs_exports()
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| H A D | si_shader_llvm_ps.c | 276 args->valid_mask = 0; in si_llvm_init_ps_export_args()
913 exp.args[exp.num - 1].valid_mask = 1; /* whether the EXEC mask is valid */ in si_llvm_build_ps_epilog()
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| H A D | gfx10_shader_ngg.c | 783 * 8 waves: valid_mask = ~0ull >> (64 - num_waves * 8) in load_vertex_counts()
784 * 4 waves: valid_mask = ~0 >> (32 - num_waves * 8) in load_vertex_counts()
787 LLVMValueRef valid_mask; in load_vertex_counts() local
792 valid_mask = LLVMBuildLShr(builder, LLVMConstInt(ctx->ac.i64, ~0ull, 0), in load_vertex_counts()
797 valid_mask = LLVMBuildLShr(builder, LLVMConstInt(ctx->ac.i32, ~0, 0), num_waves8_rev, ""); in load_vertex_counts()
822 ac_unpack_param(&ctx->ac, valid_mask, 32 * i, 32), ""); in load_vertex_counts()
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| /third_party/mesa3d/src/amd/vulkan/ |
| H A D | radv_nir_to_llvm.c | 579 args->valid_mask = 0; in si_llvm_init_export_args()
938 pos_args[0].valid_mask = 0; /* EXEC mask */ in radv_llvm_export_vs()
953 pos_args[1].valid_mask = 0; in radv_llvm_export_vs()
990 * Setting valid_mask=1 prevents it and has no other effect. in radv_llvm_export_vs()
993 pos_args[0].valid_mask = 1; in radv_llvm_export_vs()
1123 color_args[last].valid_mask = 1; /* whether the EXEC mask is valid */ in handle_fs_outputs_post()
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| /third_party/mesa3d/src/amd/compiler/ |
| H A D | aco_assembler.cpp | 572 encoding |= exp.valid_mask ? 0b1 << 12 : 0; in emit_instruction()
808 exp.valid_mask = true; in fix_exports()
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| H A D | aco_print_ir.cpp | 445 if (exp.valid_mask) in print_instr_format_specific()
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| H A D | aco_ir.h | 1661 bool valid_mask : 1;
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| H A D | aco_instruction_selection.cpp | 10913 * Setting valid_mask=1 prevents it and has no other effect.
10915 exp->valid_mask = ctx->options->gfx_level == GFX10 && is_pos && *next_pos == 0;
10963 exp->valid_mask = ctx->options->gfx_level == GFX10 && *next_pos == 0;
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| /third_party/mesa3d/src/amd/llvm/ |
| H A D | ac_llvm_build.h | 340 bool valid_mask; member
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| H A D | ac_llvm_build.c | 1987 args[5] = LLVMConstInt(ctx->i1, a->valid_mask, 0); in ac_build_export()
1996 args[7] = LLVMConstInt(ctx->i1, a->valid_mask, 0); in ac_build_export()
2013 args.valid_mask = 1; /* whether the EXEC mask is valid */ in ac_build_export_null()
4321 args->valid_mask = 1; /* whether the EXEC mask is valid */ in ac_export_mrt_z()
4488 args.valid_mask = false; in ac_build_export_prim()
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| /third_party/mesa3d/src/imagination/vulkan/ |
| H A D | pvr_private.h | 536 uint32_t valid_mask; member
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| H A D | pvr_cmd_buffer.c | 2053 descriptor_state->valid_mask |= (1u << index); in pvr_CmdBindDescriptorSets()
2830 if (!(desc_state->valid_mask & BITFIELD_BIT(desc_set_num))) { in pvr_setup_descriptor_mappings()
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| /third_party/mesa3d/src/gallium/auxiliary/draw/ |
| H A D | draw_llvm.c | 1087 LLVMValueRef offset, valid_mask; in fetch_vector() local
1098 valid_mask = lp_build_compare(gallivm, blduivec.type, in fetch_vector()
1102 offset = LLVMBuildAnd(builder, offset, valid_mask, ""); in fetch_vector()
1107 lp_build_print_value(gallivm, " valid_mask = ", valid_mask); in fetch_vector()
1139 inputs[i] = LLVMBuildAnd(builder, inputs[i], valid_mask, ""); in fetch_vector()
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| /third_party/mesa3d/src/egl/drivers/dri2/ |
| H A D | egl_dri2.c | 2969 unsigned int dri_use, valid_mask; in dri2_create_drm_image_mesa() local
2994 valid_mask = in dri2_create_drm_image_mesa()
2998 if (attrs.DRMBufferUseMESA & ~valid_mask) { in dri2_create_drm_image_mesa()
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| /third_party/node/deps/simdutf/ |
| H A D | simdutf.cpp | 18551 const __mmask16 valid_mask = uint16_t((1 << VALID_COUNT) - 1); \
18552 _mm512_mask_storeu_epi32((__m512i*)output, valid_mask, INPUT); \
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