| /third_party/ffmpeg/libavcodec/arm/ |
| H A D | ac3dsp_neon.S | 27 vabs.s16 q1, q1
29 vabs.s16 q3, q3
101 vabs.s32 q1, q0
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| H A D | sbcdsp_neon.S | 233 vabs.s32 q8, q8
235 vabs.s32 q9, q9
237 vabs.s32 q10, q10
239 vabs.s32 q11, q11
285 vabs.s32 q8, q8
286 vabs.s32 q9, q9
287 vabs.s32 q10, q10
288 vabs.s32 q11, q11
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| H A D | vp6dsp_neon.S | 39 vabs.s16 q1, q0 @ V
41 vabs.s16 d30, d28
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| H A D | hevcdsp_deblock_neon.S | 238 vabs.s16 q3, q2
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| H A D | vp3dsp_neon.S | 45 vabs.s16 q1, q0
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| H A D | rv40dsp_neon.S | 848 vabs.s16 q1, q1 @ abs(p1p2), abs(q1q2)
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| /third_party/python/Objects/ |
| H A D | complexobject.c | 132 double vabs,len,at,phase; in _Py_c_pow() local
144 vabs = hypot(a.real,a.imag); in _Py_c_pow()
145 len = pow(vabs,b.real); in _Py_c_pow()
150 phase += b.imag*log(vabs); in _Py_c_pow()
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| /third_party/node/deps/v8/src/diagnostics/arm/ |
| H A D | disasm-arm.cc | 1410 // Dd = vabs(Dm)
1411 // Sd = vabs(Sm)
1450 // vabs in DecodeTypeVFP()
1452 Format(instr, "vabs'cond.f64 'Dd, 'Dm"); in DecodeTypeVFP()
1454 Format(instr, "vabs'cond.f32 'Sd, 'Sm"); in DecodeTypeVFP()
2290 Format(instr, q ? "vabs.s'size2 'Qd, 'Qm" : "vabs.s.'size2 'Dd, 'Dm"); in DecodeAdvancedSIMDTwoOrThreeRegisters()
2292 Format(instr, q ? "vabs.f'size2 'Qd, 'Qm" : "vabs.f.'size2 'Dd, 'Dm"); in DecodeAdvancedSIMDTwoOrThreeRegisters()
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| /third_party/node/deps/v8/src/codegen/arm/ |
| H A D | assembler-arm.h | 772 void vabs(const DwVfpRegister dst, const DwVfpRegister src,
774 void vabs(const SwVfpRegister dst, const SwVfpRegister src,
883 void vabs(QwNeonRegister dst, QwNeonRegister src);
884 void vabs(NeonSize size, QwNeonRegister dst, QwNeonRegister src);
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| H A D | assembler-arm.cc | 3158 void Assembler::vabs(const DwVfpRegister dst, const DwVfpRegister src, in vabs() function in v8::internal::Assembler
3173 void Assembler::vabs(const SwVfpRegister dst, const SwVfpRegister src, in vabs() function in v8::internal::Assembler
4190 void Assembler::vabs(QwNeonRegister dst, QwNeonRegister src) { in vabs() function in v8::internal::Assembler
4191 // Qd = vabs.f<size>(Qn, Qm) SIMD floating point absolute value. in vabs()
4197 void Assembler::vabs(NeonSize size, QwNeonRegister dst, QwNeonRegister src) { in vabs() function in v8::internal::Assembler
4198 // Qd = vabs.s<size>(Qn, Qm) SIMD integer absolute value. in vabs()
4205 // Qd = vabs.f<size>(Qn, Qm) SIMD floating point negate. in vneg()
4212 // Qd = vabs.s<size>(Qn, Qm) SIMD integer negate. in vneg()
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| /third_party/node/deps/v8/src/compiler/backend/arm/ |
| H A D | code-generator-arm.cc | 1337 __ vabs(i.OutputFloatRegister(), i.InputFloatRegister(0)); in AssembleArchInstruction()
1401 __ vabs(i.OutputDoubleRegister(), i.InputDoubleRegister(0)); in AssembleArchInstruction()
1832 __ vabs(i.OutputSimd128Register().low(), i.InputSimd128Register(0).low()); in AssembleArchInstruction()
1833 __ vabs(i.OutputSimd128Register().high(), in AssembleArchInstruction()
2189 __ vabs(i.OutputSimd128Register(), i.InputSimd128Register(0)); in AssembleArchInstruction()
2459 __ vabs(Neon32, i.OutputSimd128Register(), i.InputSimd128Register(0)); in AssembleArchInstruction()
2663 __ vabs(Neon16, i.OutputSimd128Register(), i.InputSimd128Register(0)); in AssembleArchInstruction()
2818 __ vabs(Neon8, i.OutputSimd128Register(), i.InputSimd128Register(0)); in AssembleArchInstruction()
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| /third_party/node/deps/v8/src/wasm/baseline/arm/ |
| H A D | liftoff-assembler-arm.h | 1561 FP32_UNOP(f32_abs, vabs)
1568 FP64_UNOP(f64_abs, vabs)
2485 vabs(dst.low_fp(), src.low_fp()); in emit_f64x2_abs()
2486 vabs(dst.high_fp(), src.high_fp()); in emit_f64x2_abs()
2670 vabs(liftoff::GetSimd128Register(dst), liftoff::GetSimd128Register(src)); in emit_f32x4_abs()
4039 vabs(Neon8, liftoff::GetSimd128Register(dst),
4045 vabs(Neon16, liftoff::GetSimd128Register(dst),
4051 vabs(Neon32, liftoff::GetSimd128Register(dst),
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| /third_party/vixl/src/aarch32/ |
| H A D | assembler-aarch32.h | 3833 void vabs(Condition cond, DataType dt, DRegister rd, DRegister rm);
3834 void vabs(DataType dt, DRegister rd, DRegister rm) { vabs(al, dt, rd, rm); } in vabs() function in vixl::aarch32::Assembler
3836 void vabs(Condition cond, DataType dt, QRegister rd, QRegister rm);
3837 void vabs(DataType dt, QRegister rd, QRegister rm) { vabs(al, dt, rd, rm); } in vabs() function in vixl::aarch32::Assembler
3839 void vabs(Condition cond, DataType dt, SRegister rd, SRegister rm);
3840 void vabs(DataType dt, SRegister rd, SRegister rm) { vabs(al, dt, rd, rm); } in vabs() function in vixl::aarch32::Assembler
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| H A D | disasm-aarch32.h | 1482 void vabs(Condition cond, DataType dt, DRegister rd, DRegister rm);
1484 void vabs(Condition cond, DataType dt, QRegister rd, QRegister rm);
1486 void vabs(Condition cond, DataType dt, SRegister rd, SRegister rm);
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| H A D | disasm-aarch32.cc | 3774 void Disassembler::vabs(Condition cond, in vabs() function in vixl::aarch32::Disassembler
3783 void Disassembler::vabs(Condition cond, in vabs() function in vixl::aarch32::Disassembler
3792 void Disassembler::vabs(Condition cond, in vabs() function in vixl::aarch32::Disassembler
[all...] |
| H A D | assembler-aarch32.cc | 14134 void Assembler::vabs(Condition cond, DataType dt, DRegister rd, DRegister rm) { in vabs() function in vixl::aarch32::Assembler
14172 Delegate(kVabs, &Assembler::vabs, cond, dt, rd, rm); in vabs()
14175 void Assembler::vabs(Condition cond, DataType dt, QRegister rd, QRegister rm) { in vabs() function in vixl::aarch32::Assembler
14201 Delegate(kVabs, &Assembler::vabs, cond, dt, rd, rm); in vabs()
14204 void Assembler::vabs(Condition cond, DataType dt, SRegister rd, SRegister rm) { in vabs() function in vixl::aarch32::Assembler
14222 Delegate(kVabs, &Assembler::vabs, cond, dt, rd, rm); in vabs()
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| H A D | macro-assembler-aarch32.h | 6532 vabs(cond, dt, rd, rm); in MacroAssembler()
6547 vabs(cond, dt, rd, rm); in MacroAssembler()
6562 vabs(cond, dt, rd, rm); in MacroAssembler()
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