| /third_party/ffmpeg/libavcodec/arm/ |
| H A D | mlpdsp_armv6.S | 138 uxtb SHIFT0, SHIFT4, ror #0
139 uxtb SHIFT1, SHIFT4, ror #8
140 uxtb SHIFT2, SHIFT4, ror #16
141 uxtb SHIFT3, SHIFT4, ror #24
143 uxtb SHIFT0, SHIFT5, ror #0
144 uxtb SHIFT1, SHIFT5, ror #8
145 uxtb SHIFT2, SHIFT5, ror #16
146 uxtb SHIFT3, SHIFT5, ror #24
187 uxtb SHIFT0, SHIFT4, ror #0
188 uxtb SHIFT
[all...] |
| /third_party/optimized-routines/string/arm/ |
| H A D | strcmp.S | 280 uxtb tmp1, data1, ror #BYTE1_OFFSET
287 uxtb tmp1, data1, ror #BYTE2_OFFSET
294 uxtb tmp1, data1, ror #BYTE3_OFFSET
303 uxtb tmp1, data1, ror #BYTE2_OFFSET
310 uxtb tmp1, data1, ror #BYTE3_OFFSET
|
| H A D | strcmp-armv6m.S | 58 uxtb r0, r2
59 uxtb r1, r3
|
| H A D | memset.S | 63 @ POSIX says that ch is cast to an unsigned char. A uxtb is one
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| /third_party/node/deps/v8/src/diagnostics/arm/ |
| H A D | disasm-arm.cc | 1218 Format(instr, "uxtb'cond 'rd, 'rm"); in DecodeType3()
1221 Format(instr, "uxtb'cond 'rd, 'rm, ror #8"); in DecodeType3()
1224 Format(instr, "uxtb'cond 'rd, 'rm, ror #16"); in DecodeType3()
1227 Format(instr, "uxtb'cond 'rd, 'rm, ror #24"); in DecodeType3()
|
| /third_party/vixl/test/aarch32/ |
| H A D | test-assembler-cond-rd-operand-rn-t32.cc | 63 M(uxtb) \
347 #include "aarch32/traces/assembler-cond-rd-operand-rn-uxtb-t32.h"
|
| H A D | test-assembler-cond-rd-operand-rn-a32.cc | 63 M(uxtb) \
1122 #include "aarch32/traces/assembler-cond-rd-operand-rn-uxtb-a32.h"
|
| H A D | test-assembler-cond-rd-operand-rn-ror-amount-a32.cc | 55 M(uxtb) \
1320 #include "aarch32/traces/assembler-cond-rd-operand-rn-ror-amount-uxtb-a32.h"
|
| H A D | test-assembler-cond-rd-operand-rn-ror-amount-t32.cc | 55 M(uxtb) \
1208 #include "aarch32/traces/assembler-cond-rd-operand-rn-ror-amount-uxtb-t32.h"
|
| /third_party/vixl/src/aarch32/ |
| H A D | assembler-aarch32.h | 3766 void uxtb(Condition cond,
3770 void uxtb(Register rd, const Operand& operand) { in uxtb() function in vixl::aarch32::Assembler
3771 uxtb(al, Best, rd, operand); in uxtb()
3773 void uxtb(Condition cond, Register rd, const Operand& operand) { in uxtb() function in vixl::aarch32::Assembler
3774 uxtb(cond, Best, rd, operand); in uxtb()
3776 void uxtb(EncodingSize size, Register rd, const Operand& operand) { in uxtb() function in vixl::aarch32::Assembler
3777 uxtb(al, size, rd, operand); in uxtb()
|
| H A D | disasm-aarch32.h | 1452 void uxtb(Condition cond,
|
| H A D | disasm-aarch32.cc | 3688 void Disassembler::uxtb(Condition cond, in uxtb() function in vixl::aarch32::Disassembler
8090 uxtb(CurrentCond(), in DecodeT32()
21089 uxtb(CurrentCond(), in DecodeT32()
21098 uxtb(CurrentCond(), in DecodeT32()
[all...] |
| /third_party/node/deps/v8/src/codegen/arm64/ |
| H A D | macro-assembler-arm64-inl.h | 1021 uxtb(rd, rn); in Uxtb()
|
| H A D | assembler-arm64.h | 675 void uxtb(const Register& rd, const Register& rn) { ubfm(rd, rn, 0, 7); }
|
| /third_party/node/deps/v8/src/codegen/arm/ |
| H A D | assembler-arm.h | 582 void uxtb(Register dst, Register src, int rotate = 0, Condition cond = al);
|
| H A D | assembler-arm.cc | 1980 void Assembler::uxtb(Register dst, Register src, int rotate, Condition cond) { in uxtb() function in v8::internal::Assembler
|
| /third_party/vixl/test/aarch64/ |
| H A D | test-api-movprfx-aarch64.cc | 319 __ uxtb(z23.VnS(), p7.Merging(), z23.VnS()); in TEST()
861 __ uxtb(z29.VnS(), p4.Merging(), z31.VnS()); in TEST()
1684 __ uxtb(z31.VnS(), p0.Merging(), z3.VnS()); in TEST()
|
| H A D | test-disasm-aarch64.cc | 81 COMPARE_MACRO(Mov(w10, Operand(w11, UXTB)), "uxtb w10, w11"); in TEST()
332 COMPARE(add(w0, w1, Operand(w2, UXTB)), "add w0, w1, w2, uxtb"); in TEST()
333 COMPARE(adds(x3, x4, Operand(w5, UXTB, 1)), "adds x3, x4, w5, uxtb #1"); in TEST()
342 COMPARE(cmn(w0, Operand(w1, UXTB, 2)), "cmn w0, w1, uxtb #2"); in TEST()
345 COMPARE(add(w0, wsp, Operand(w1, UXTB)), "add w0, wsp, w1, uxtb"); in TEST()
358 COMPARE(sub(w0, w1, Operand(w2, UXTB)), "sub w0, w1, w2, uxtb"); in TEST()
359 COMPARE(subs(x3, x4, Operand(w5, UXTB, 1)), "subs x3, x4, w5, uxtb #1"); in TEST()
371 COMPARE(sub(w0, wsp, Operand(w1, UXTB)), "sub w0, wsp, w1, uxtb"); in TEST()
537 COMPARE(uxtb(w10, w11), "uxtb w1 in TEST()
[all...] |
| H A D | test-trace-aarch64.cc | 366 __ uxtb(w28, w29); in GenerateTestSequenceBase()
367 __ uxtb(x2, x3); in GenerateTestSequenceBase()
|
| H A D | test-disasm-sve-aarch64.cc | 2992 COMPARE(uxtb(z23.VnH(), p3.Merging(), z21.VnH()), "uxtb z23.h, p3/m, z21.h"); in TEST()
2993 COMPARE(uxtb(z0.VnS(), p2.Merging(), z13.VnS()), "uxtb z0.s, p2/m, z13.s"); in TEST()
2994 COMPARE(uxtb(z1.VnD(), p3.Merging(), z13.VnD()), "uxtb z1.d, p3/m, z13.d"); in TEST()
3007 COMPARE(dci(0x0411a000), "unallocated (Unallocated)"); // uxtb b in TEST()
|
| /third_party/vixl/src/aarch64/ |
| H A D | assembler-aarch64.h | 890 void uxtb(const Register& rd, const Register& rn) { ubfm(rd, rn, 0, 7); }
5843 void uxtb(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn);
|
| H A D | macro-assembler-aarch64.h | 2793 uxtb(rd, rn); in Uxtb()
6461 uxtb(zd, pg, zn); in Uxtb()
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| H A D | assembler-sve-aarch64.cc | 3514 void Assembler::uxtb(const ZRegister& zd, in uxtb() function in vixl::aarch64::Assembler
|
| /third_party/node/deps/v8/src/compiler/backend/arm/ |
| H A D | code-generator-arm.cc | 1174 __ uxtb(i.OutputRegister(), i.InputRegister(0), i.InputInt32(1)); in AssembleArchInstruction()
3374 __ uxtb(i.TempRegister(2), i.InputRegister(2)); in AssembleArchInstruction()
3381 __ uxtb(i.TempRegister(2), i.InputRegister(2)); in AssembleArchInstruction()
|
| /third_party/node/deps/v8/src/wasm/baseline/arm/ |
| H A D | liftoff-assembler-arm.h | 1295 uxtb(expected.gp(), expected.gp()); in AtomicCompareExchange()
|