| /third_party/ffmpeg/libavcodec/aarch64/ |
| H A D | h264dsp_neon.S | 82 usubw v4.8H, v4.8H, v16.8B
88 usubw v4.8H, v4.8H, v2.8B
391 usubw v4.8H, v4.8H, v16.8B
398 usubw v4.8H, v4.8H, v2.8B
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| H A D | vp9lpf_neon.S | 76 usubw \dst1, \in1, \in3\().8b
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| /third_party/node/deps/v8/src/codegen/arm64/ |
| H A D | assembler-arm64.h | 1294 void usubw(const VRegister& vd, const VRegister& vn, const VRegister& vm);
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| H A D | macro-assembler-arm64.h | 478 V(usubw, Usubw) \
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| H A D | assembler-arm64.cc | 1843 void Assembler::usubw(const VRegister& vd, const VRegister& vn, in usubw() function in v8::internal::Assembler
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| /third_party/vixl/test/aarch64/ |
| H A D | test-trace-aarch64.cc | 2475 __ usubw(v9.V2D(), v20.V2D(), v30.V2S()); in GenerateTestSequenceNEON()
2476 __ usubw(v20.V4S(), v16.V4S(), v23.V4H()); in GenerateTestSequenceNEON()
2477 __ usubw(v25.V8H(), v8.V8H(), v29.V8B()); in GenerateTestSequenceNEON()
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| H A D | test-cpu-features-aarch64.cc | 2738 TEST_NEON(usubw_0, usubw(v0.V8H(), v1.V8H(), v2.V8B()))
2739 TEST_NEON(usubw_1, usubw(v0.V4S(), v1.V4S(), v2.V4H()))
2740 TEST_NEON(usubw_2, usubw(v0.V2D(), v1.V2D(), v2.V2S()))
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| H A D | test-simulator-aarch64.cc | 4745 DEFINE_TEST_NEON_3DIFF_WIDE(usubw, Basic)
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| /third_party/node/deps/v8/src/execution/arm64/ |
| H A D | simulator-arm64.h | 1845 LogicVRegister usubw(VectorFormat vform, LogicVRegister dst,
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| H A D | simulator-arm64.cc | 4564 usubw(vf_l, rd, rn, rm);
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| H A D | simulator-logic-arm64.cc | 2417 LogicVRegister Simulator::usubw(VectorFormat vform, LogicVRegister dst, in usubw() function in v8::internal::Simulator
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| /third_party/vixl/src/aarch64/ |
| H A D | simulator-aarch64.cc | 2601 usubw(vform, zd, zn, zm_b); in Simulator()
2604 usubw(vform, zd, zn, zm_t); in Simulator()
7828 usubw(vf_l, rd, rn, rm); in Simulator()
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| H A D | simulator-aarch64.h | 4043 LogicVRegister usubw(VectorFormat vform,
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| H A D | assembler-aarch64.h | 3165 void usubw(const VRegister& vd, const VRegister& vn, const VRegister& vm);
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| H A D | assembler-aarch64.cc | 3072 void Assembler::usubw(const VRegister& vd,
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| H A D | logic-aarch64.cc | 3596 LogicVRegister Simulator::usubw(VectorFormat vform,
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| H A D | macro-assembler-aarch64.h | 2979 V(usubw, Usubw) \
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