Home
last modified time | relevance | path

Searched refs:uqshl (Results 1 - 19 of 19) sorted by relevance

/third_party/vixl/test/aarch64/
H A Dtest-trace-aarch64.cc2343 __ uqshl(b13, b0, b23); in GenerateTestSequenceNEON()
2344 __ uqshl(b9, b17, 4); in GenerateTestSequenceNEON()
2345 __ uqshl(d23, d6, d4); in GenerateTestSequenceNEON()
2346 __ uqshl(d8, d11, 44); in GenerateTestSequenceNEON()
2347 __ uqshl(h19, h13, h15); in GenerateTestSequenceNEON()
2348 __ uqshl(h25, h26, 6); in GenerateTestSequenceNEON()
2349 __ uqshl(s4, s24, s10); in GenerateTestSequenceNEON()
2350 __ uqshl(s19, s14, 1); in GenerateTestSequenceNEON()
2351 __ uqshl(v14.V16B(), v30.V16B(), v25.V16B()); in GenerateTestSequenceNEON()
2352 __ uqshl(v in GenerateTestSequenceNEON()
[all...]
H A Dtest-cpu-features-aarch64.cc2606 TEST_NEON(uqshl_0, uqshl(v0.V8B(), v1.V8B(), 7))
2607 TEST_NEON(uqshl_1, uqshl(v0.V16B(), v1.V16B(), 2))
2608 TEST_NEON(uqshl_2, uqshl(v0.V4H(), v1.V4H(), 4))
2609 TEST_NEON(uqshl_3, uqshl(v0.V8H(), v1.V8H(), 4))
2610 TEST_NEON(uqshl_4, uqshl(v0.V2S(), v1.V2S(), 1))
2611 TEST_NEON(uqshl_5, uqshl(v0.V4S(), v1.V4S(), 2))
2612 TEST_NEON(uqshl_6, uqshl(v0.V2D(), v1.V2D(), 28))
2613 TEST_NEON(uqshl_7, uqshl(b0, b1, 6))
2614 TEST_NEON(uqshl_8, uqshl(h0, h1, 15))
2615 TEST_NEON(uqshl_9, uqshl(s
[all...]
H A Dtest-simulator-aarch64.cc4645 DEFINE_TEST_NEON_3SAME(uqshl, Basic)
4702 DEFINE_TEST_NEON_3SAME_SCALAR(uqshl, Basic)
4795 DEFINE_TEST_NEON_2OPIMM(uqshl, Basic, TypeWidthFromZero)
4827 DEFINE_TEST_NEON_2OPIMM_SCALAR(uqshl, Basic, TypeWidthFromZero)
H A Dtest-disasm-sve-aarch64.cc6564 COMPARE(uqshl(z29.VnB(), p7.Merging(), z29.VnB(), 0), in TEST()
6565 "uqshl z29.b, p7/m, z29.b, #0"); in TEST()
6566 COMPARE(uqshl(z29.VnB(), p7.Merging(), z29.VnB(), 2), in TEST()
6567 "uqshl z29.b, p7/m, z29.b, #2"); in TEST()
6568 COMPARE(uqshl(z29.VnB(), p7.Merging(), z29.VnB(), 5), in TEST()
6569 "uqshl z29.b, p7/m, z29.b, #5"); in TEST()
6570 COMPARE(uqshl(z29.VnB(), p7.Merging(), z29.VnB(), 7), in TEST()
6571 "uqshl z29.b, p7/m, z29.b, #7"); in TEST()
6572 COMPARE(uqshl(z29.VnH(), p7.Merging(), z29.VnH(), 0), in TEST()
6573 "uqshl z2 in TEST()
[all...]
H A Dtest-api-movprfx-aarch64.cc2358 __ uqshl(z29.VnB(), p7.Merging(), z29.VnB(), 0); in TEST()
2361 __ uqshl(z29.VnB(), p7.Merging(), z29.VnB(), z30.VnB()); in TEST()
3539 __ uqshl(z29.VnB(), p7.Merging(), z29.VnB(), z29.VnB()); in TEST()
3679 __ uqshl(z29.VnB(), p7.Merging(), z29.VnB(), 0); in TEST()
3682 __ uqshl(z29.VnB(), p7.Merging(), z29.VnB(), z30.VnB()); in TEST()
/third_party/node/deps/v8/src/codegen/arm64/
H A Dassembler-arm64.h1158 void uqshl(const VRegister& vd, const VRegister& vn, const VRegister& vm);
1940 void uqshl(const VRegister& vd, const VRegister& vn, int shift);
H A Dmacro-assembler-arm64.h470 V(uqshl, Uqshl) \
1242 V(uqshl, Uqshl) \
H A Dassembler-arm64.cc1654 void Assembler::uqshl(const VRegister& vd, const VRegister& vn, int shift) { in uqshl() function in v8::internal::Assembler
3108 V(uqshl, NEON_UQSHL, true) \
/third_party/vixl/src/aarch64/
H A Dassembler-aarch64.h2719 void uqshl(const VRegister& vd, const VRegister& vn, const VRegister& vm);
2998 void uqshl(const VRegister& vd, const VRegister& vn, int shift);
6766 void uqshl(const ZRegister& zd,
6772 void uqshl(const ZRegister& zd,
H A Dmacro-assembler-sve-aarch64.cc682 V(Uqshl, uqshl) \
H A Dmacro-assembler-aarch64.h2972 V(uqshl, Uqshl) \
3183 V(uqshl, Uqshl) \
7477 uqshl(zd, pg, zd, shift); in Uqshl()
H A Dsimulator-aarch64.cc3534 uqshl(vform, result, zdn, left_shift_dist); in Simulator()
9330 uqshl(vf, rd, rn, left_shift); in Simulator()
9469 uqshl(vf, rd, rn, left_shift); in Simulator()
H A Dsimulator-aarch64.h4224 LogicVRegister uqshl(VectorFormat vform,
H A Dassembler-aarch64.cc4212 V(uqshl, NEON_UQSHL, true) \
5568 void Assembler::uqshl(const VRegister& vd, const VRegister& vn, int shift) {
H A Dassembler-sve-aarch64.cc9373 void Assembler::uqshl(const ZRegister& zd, in uqshl() function in vixl::aarch64::Assembler
9390 void Assembler::uqshl(const ZRegister& zd, in uqshl() function in vixl::aarch64::Assembler
H A Dlogic-aarch64.cc1693 LogicVRegister Simulator::uqshl(VectorFormat vform,
/third_party/node/deps/v8/src/execution/arm64/
H A Dsimulator-arm64.h1931 LogicVRegister uqshl(VectorFormat vform, LogicVRegister dst,
H A Dsimulator-arm64.cc5747 uqshl(vf, rd, rn, left_shift);
5882 uqshl(vf, rd, rn, left_shift);
H A Dsimulator-logic-arm64.cc1417 LogicVRegister Simulator::uqshl(VectorFormat vform, LogicVRegister dst, in uqshl() function in v8::internal::Simulator

Completed in 135 milliseconds