| /third_party/ffmpeg/libavcodec/aarch64/ |
| H A D | h264dsp_neon.S | 494 uqrshrn v24.8b, v20.8h, #2
495 uqrshrn v25.8b, v22.8h, #2
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| /third_party/vixl/test/aarch64/ |
| H A D | test-trace-aarch64.cc | 2334 __ uqrshrn(b11, h26, 4); in GenerateTestSequenceNEON()
2335 __ uqrshrn(h7, s30, 5); in GenerateTestSequenceNEON()
2336 __ uqrshrn(s10, d8, 21); in GenerateTestSequenceNEON()
2337 __ uqrshrn(v15.V2S(), v6.V2D(), 11); in GenerateTestSequenceNEON()
2338 __ uqrshrn(v5.V4H(), v26.V4S(), 12); in GenerateTestSequenceNEON()
2339 __ uqrshrn(v28.V8B(), v25.V8H(), 5); in GenerateTestSequenceNEON()
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| H A D | test-cpu-features-aarch64.cc | 2597 TEST_NEON(uqrshrn_0, uqrshrn(v0.V8B(), v1.V8H(), 5))
2598 TEST_NEON(uqrshrn_1, uqrshrn(v0.V4H(), v1.V4S(), 4))
2599 TEST_NEON(uqrshrn_2, uqrshrn(v0.V2S(), v1.V2D(), 23))
2603 TEST_NEON(uqrshrn_3, uqrshrn(b0, h1, 4))
2604 TEST_NEON(uqrshrn_4, uqrshrn(h0, s1, 4))
2605 TEST_NEON(uqrshrn_5, uqrshrn(s0, d1, 7))
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| H A D | test-simulator-aarch64.cc | 4799 DEFINE_TEST_NEON_2OPIMM_NARROW(uqrshrn, Basic, TypeWidth)
4831 DEFINE_TEST_NEON_2OPIMM_SCALAR_NARROW(uqrshrn, Basic, TypeWidth)
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| /third_party/node/deps/v8/src/codegen/arm64/ |
| H A D | assembler-arm64.h | 1390 void uqrshrn(const VRegister& vd, const VRegister& vn, int shift);
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| H A D | macro-assembler-arm64.h | 1240 V(uqrshrn, Uqrshrn) \
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| H A D | assembler-arm64.cc | 1809 void Assembler::uqrshrn(const VRegister& vd, const VRegister& vn, int shift) { in uqrshrn() function in v8::internal::Assembler
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| /third_party/node/deps/v8/src/execution/arm64/ |
| H A D | simulator-arm64.h | 1969 LogicVRegister uqrshrn(VectorFormat vform, LogicVRegister dst,
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| H A D | simulator-arm64.cc | 5783 uqrshrn(vf, rd, rn, right_shift);
5937 uqrshrn(vf, rd, rn, right_shift);
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| H A D | simulator-logic-arm64.cc | 2239 LogicVRegister Simulator::uqrshrn(VectorFormat vform, LogicVRegister dst, in uqrshrn() function in v8::internal::Simulator
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| /third_party/vixl/src/aarch64/ |
| H A D | simulator-aarch64.cc | 2711 uqrshrn(vform, result, zn, right_shift_dist); in Simulator()
9366 uqrshrn(vf, rd, rn, right_shift); in Simulator()
9524 uqrshrn(vf, rd, rn, right_shift); in Simulator()
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| H A D | simulator-aarch64.h | 4292 LogicVRegister uqrshrn(VectorFormat vform,
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| H A D | assembler-aarch64.h | 3261 void uqrshrn(const VRegister& vd, const VRegister& vn, int shift);
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| H A D | assembler-aarch64.cc | 5787 void Assembler::uqrshrn(const VRegister& vd, const VRegister& vn, int shift) {
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| H A D | logic-aarch64.cc | 3368 LogicVRegister Simulator::uqrshrn(VectorFormat vform,
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| H A D | macro-assembler-aarch64.h | 3181 V(uqrshrn, Uqrshrn) \
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