| /third_party/optimized-routines/string/aarch64/ |
| H A D | strlen.S | 147 uminp maskv.16b, datav1.16b, datav2.16b
148 uminp maskv.16b, maskv.16b, maskv.16b
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| H A D | strrchr.S | 108 uminp vend1.16b, vdata1.16b, vdata2.16b
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| /third_party/vixl/test/aarch64/ |
| H A D | test-trace-aarch64.cc | 2270 __ uminp(v5.V16B(), v1.V16B(), v23.V16B()); in GenerateTestSequenceNEON()
2271 __ uminp(v7.V2S(), v26.V2S(), v30.V2S()); in GenerateTestSequenceNEON()
2272 __ uminp(v9.V4H(), v5.V4H(), v25.V4H()); in GenerateTestSequenceNEON()
2273 __ uminp(v23.V4S(), v10.V4S(), v1.V4S()); in GenerateTestSequenceNEON()
2274 __ uminp(v4.V8B(), v29.V8B(), v14.V8B()); in GenerateTestSequenceNEON()
2275 __ uminp(v21.V8H(), v0.V8H(), v14.V8H()); in GenerateTestSequenceNEON()
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| H A D | test-cpu-features-aarch64.cc | 2524 TEST_NEON(uminp_0, uminp(v0.V8B(), v1.V8B(), v2.V8B()))
2525 TEST_NEON(uminp_1, uminp(v0.V16B(), v1.V16B(), v2.V16B()))
2526 TEST_NEON(uminp_2, uminp(v0.V4H(), v1.V4H(), v2.V4H()))
2527 TEST_NEON(uminp_3, uminp(v0.V8H(), v1.V8H(), v2.V8H()))
2528 TEST_NEON(uminp_4, uminp(v0.V2S(), v1.V2S(), v2.V2S()))
2529 TEST_NEON(uminp_5, uminp(v0.V4S(), v1.V4S(), v2.V4S()))
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| H A D | test-api-movprfx-aarch64.cc | 2310 __ uminp(z10.VnB(), p0.Merging(), z10.VnB(), z22.VnB()); in TEST()
3096 __ uminp(z10.VnB(), p0.Merging(), z10.VnB(), z22.VnB()); in TEST()
3491 __ uminp(z10.VnB(), p0.Merging(), z10.VnB(), z10.VnB()); in TEST()
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| H A D | test-disasm-sve-aarch64.cc | 6878 COMPARE(uminp(z10.VnB(), p0.Merging(), z10.VnB(), z22.VnB()), in TEST()
6879 "uminp z10.b, p0/m, z10.b, z22.b"); in TEST()
6880 COMPARE(uminp(z10.VnD(), p0.Merging(), z10.VnD(), z22.VnD()), in TEST()
6881 "uminp z10.d, p0/m, z10.d, z22.d"); in TEST()
6882 COMPARE(uminp(z10.VnH(), p0.Merging(), z10.VnH(), z22.VnH()), in TEST()
6883 "uminp z10.h, p0/m, z10.h, z22.h"); in TEST()
6884 COMPARE(uminp(z10.VnS(), p0.Merging(), z10.VnS(), z22.VnS()), in TEST()
6885 "uminp z10.s, p0/m, z10.s, z22.s"); in TEST()
6911 "uminp z4.b, p1/m, z4.b, z31.b"); in TEST()
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| H A D | test-simulator-aarch64.cc | 4656 DEFINE_TEST_NEON_3SAME_NO2D(uminp, Basic)
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| /third_party/node/deps/v8/src/codegen/arm64/ |
| H A D | assembler-arm64.h | 1324 void uminp(const VRegister& vd, const VRegister& vn, const VRegister& vm);
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| H A D | macro-assembler-arm64.h | 460 V(uminp, Uminp) \
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| H A D | assembler-arm64.cc | 3086 V(uminp, NEON_UMINP, vd.IsVector() && !vd.IsLaneSizeD()) \
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| /third_party/vixl/src/aarch64/ |
| H A D | macro-assembler-sve-aarch64.cc | 641 V(Uminp, uminp) \
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| H A D | assembler-aarch64.h | 3195 void uminp(const VRegister& vd, const VRegister& vn, const VRegister& vm);
6679 void uminp(const ZRegister& zd,
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| H A D | simulator-aarch64.h | 4089 LogicVRegister uminp(VectorFormat vform,
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| H A D | simulator-aarch64.cc | 3473 uminp(vform, result, zdn, zm); in Simulator()
7523 uminp(vf, rd, rn, rm); in Simulator()
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| H A D | assembler-aarch64.cc | 4190 V(uminp, NEON_UMINP, vd.IsVector() && !vd.IsLaneSizeD()) \
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| H A D | assembler-sve-aarch64.cc | 9204 void Assembler::uminp(const ZRegister& zd, in uminp() function in vixl::aarch64::Assembler
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| H A D | logic-aarch64.cc | 1435 LogicVRegister Simulator::uminp(VectorFormat vform, in uminp() function in vixl::aarch64::Simulator
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| H A D | macro-assembler-aarch64.h | 2963 V(uminp, Uminp) \
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| /third_party/node/deps/v8/src/execution/arm64/ |
| H A D | simulator-arm64.h | 1869 LogicVRegister uminp(VectorFormat vform, LogicVRegister dst,
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| H A D | simulator-arm64.cc | 4353 uminp(vf, rd, rn, rm);
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| H A D | simulator-logic-arm64.cc | 1305 LogicVRegister Simulator::uminp(VectorFormat vform, LogicVRegister dst, in uminp() function in v8::internal::Simulator
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