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Searched refs:uimm (Results 1 - 14 of 14) sorted by relevance

/third_party/pcre2/pcre2/src/sljit/
H A DsljitNativeMIPS_64.c35 sljit_uw uimm; in load_immediate() local
49 uimm = (sljit_uw)imm; in load_immediate()
51 uimm = ~(sljit_uw)imm; in load_immediate()
55 while (!(uimm & 0xff00000000000000l)) { in load_immediate()
57 uimm <<= 8; in load_immediate()
60 if (!(uimm & 0xf000000000000000l)) { in load_immediate()
62 uimm <<= 4; in load_immediate()
65 if (!(uimm & 0xc000000000000000l)) { in load_immediate()
67 uimm <<= 2; in load_immediate()
70 if ((sljit_sw)uimm < in load_immediate()
[all...]
H A DsljitNativeARM_64.c444 sljit_uw mask, uimm; in logical_imm() local
458 uimm = (sljit_uw)imm; in logical_imm()
466 if ((uimm & mask) != ((uimm >> len) & mask)) in logical_imm()
474 if (uimm & 0x1) { in logical_imm()
476 uimm = ~uimm; in logical_imm()
480 uimm &= ((sljit_uw)1 << len) - 1; in logical_imm()
483 COUNT_TRAILING_ZERO(uimm, right); in logical_imm()
486 imm = (sljit_sw)~uimm; in logical_imm()
[all...]
H A DsljitNativeARM_T2_32.c59 #define NEGATE(uimm) ((sljit_uw)-(sljit_sw)(uimm))
/third_party/mesa3d/src/freedreno/afuc/
H A Demu.c137 instr->alui.uimm); in emu_instr()
142 uint32_t val = instr->movi.uimm << instr->movi.shift; in emu_instr()
193 emu_set_gpr_reg(emu, instr->control.src2, src2 + instr->control.uimm); in emu_instr()
198 emu_set_control_reg(emu, src2 + instr->control.uimm, src1); in emu_instr()
205 emu_set_gpr_reg(emu, instr->control.src2, src2 + instr->control.uimm); in emu_instr()
211 emu_get_control_reg(emu, src2 + instr->control.uimm)); in emu_instr()
216 instr->control.uimm; in emu_instr()
220 emu_set_gpr_reg(emu, instr->control.src2, src2 + instr->control.uimm); in emu_instr()
233 instr->control.uimm; in emu_instr()
237 emu_set_gpr_reg(emu, instr->control.src2, src2 + instr->control.uimm); in emu_instr()
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H A Ddisasm.c384 printf("0x%04x", instr->alui.uimm); in disasm_instr()
385 print_gpu_reg(instr->alui.uimm); in disasm_instr()
400 printf(", 0x%04x", instr->movi.uimm); in disasm_instr()
405 uint32_t val = (uint32_t)instr->movi.uimm << (uint32_t)instr->movi.shift; in disasm_instr()
419 ((instr->movi.uimm & 0xff00) == 0x7000)) { in disasm_instr()
422 opc = instr->movi.uimm & 0x7f; in disasm_instr()
431 if (1 || p == ((instr->movi.uimm >> 7) & 0x1)) { in disasm_instr()
442 print_gpu_reg((uint32_t)instr->movi.uimm << (uint32_t)instr->movi.shift); in disasm_instr()
591 print_control_reg(instr->control.uimm); in disasm_instr()
593 printf("0x%03x", instr->control.uimm); in disasm_instr()
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H A Dafuc.h147 uint32_t uimm : 16; member
153 uint32_t uimm : 16; member
168 uint32_t uimm : 12; member
172 * 0x4 - post-increment src2 by uimm (need to confirm this is also
181 uint32_t src2 : 5; /* read or write address is src2+uimm */
H A Dasm.c196 instr.alui.uimm = ai->immed; in emit_instructions()
217 instr.movi.uimm = ai->immed; in emit_instructions()
226 instr.movi.uimm = resolve_label(ai->label); in emit_instructions()
269 instr.control.uimm = ai->immed; in emit_instructions()
/third_party/mesa3d/src/freedreno/ir3/
H A Dir3_cp.c599 uint32_t uimm = instr->srcs[0]->uim_val; in instr_cp() local
601 uimm &= 0xffff; in instr_cp()
602 instr->srcs[0]->uim_val = uimm; in instr_cp()
H A Dir3_spill.c44 uint32_t uimm; member
694 src->uim_val = val->uimm; in set_src_val()
1274 dst_interval->dst.uimm = src->uim_val; in handle_pcopy()
/third_party/elfutils/libcpu/
H A Driscv_disasm.c299 uint16_t uimm = (((first << 4) & 0xc0) in riscv_disasm() local
304 snprintf (addrbuf, sizeof (addrbuf), "%" PRIu16 "(%s)", uimm, REG (2)); in riscv_disasm()
/third_party/node/deps/v8/src/diagnostics/riscv64/
H A Ddisasm-riscv64.cc834 DCHECK(STRING_STARTS_WITH(format, "uimm")); in FormatOption()
1612 Format(instr, "csrwi 'csr, 'uimm"); in DecodeIType()
1614 Format(instr, "csrrwi 'rd, 'csr, 'uimm"); in DecodeIType()
1618 Format(instr, "csrsi 'csr, 'uimm"); in DecodeIType()
1620 Format(instr, "csrrsi 'rd, 'csr, 'uimm"); in DecodeIType()
1624 Format(instr, "csrci 'csr, 'uimm"); in DecodeIType()
1626 Format(instr, "csrrci 'rd, 'csr, 'uimm"); in DecodeIType()
2642 Format(instr, "vsetivli 'rd, 'uimm, 'sew, 'lmul"); in DecodeVType()
/third_party/node/deps/v8/src/codegen/riscv64/
H A Dconstants-riscv64.h1736 // | funct3 | uimm[5] | rs1 | uimm[4:2|7:6] | opcode |
1746 // | funct3 | uimm[5] | rs1 | uimm[4:3|8:6] | opcode |
1756 // | funct3 | uimm[5:2|7:6] | rs2 | opcode |
1765 // | funct3 | uimm[5:3|8:6] | rs2 | opcode |
1872 uint32_t uimm = Bits & kRvvUimmMask;
1873 return uimm >> kRvvUimmShift;
H A Dassembler-riscv64.cc2878 void Assembler::vsetivli(Register rd, uint8_t uimm, VSew vsew, Vlmul vlmul, in vsetivli() argument
2880 DCHECK(is_uint5(uimm)); in vsetivli()
2883 ((uimm & 0x1F) << kRvvUimmShift) | in vsetivli()
H A Dassembler-riscv64.h1477 void vsetivli(Register rd, uint8_t uimm, VSew vsew, Vlmul vlmul,

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