Searched refs:uaddv (Results 1 - 7 of 7) sorted by relevance
| /third_party/vixl/test/aarch64/ |
| H A D | test-disasm-sve-aarch64.cc | 2933 COMPARE(uaddv(d13, p0, z15.VnB()), "uaddv d13, p0, z15.b"); in TEST()
2934 COMPARE(uaddv(d15, p2, z20.VnH()), "uaddv d15, p2, z20.h"); in TEST()
2935 COMPARE(uaddv(d17, p4, z25.VnS()), "uaddv d17, p4, z25.s"); in TEST()
2936 COMPARE(uaddv(d19, p6, z30.VnD()), "uaddv d19, p6, z30.d"); in TEST()
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| /third_party/vixl/src/aarch64/ |
| H A D | simulator-aarch64.h | 4767 LogicVRegister uaddv(VectorFormat vform,
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| H A D | assembler-aarch64.h | 5694 void uaddv(const VRegister& dd, const PRegister& pg, const ZRegister& zn);
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| H A D | assembler-sve-aarch64.cc | 3325 void Assembler::uaddv(const VRegister& dd, in uaddv() function in vixl::aarch64::Assembler
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| H A D | logic-aarch64.cc | 2181 LogicVRegister Simulator::uaddv(VectorFormat vform,
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| H A D | macro-assembler-aarch64.h | 6264 uaddv(dd, pg, zn); in Uaddv()
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| H A D | simulator-aarch64.cc | 11684 uaddv(vform, vd, pg, zn); in Simulator()
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