| /third_party/vixl/test/aarch64/ |
| H A D | test-trace-aarch64.cc | 2206 __ uadalp(v9.V1D(), v15.V2S()); in GenerateTestSequenceNEON()
2207 __ uadalp(v14.V2D(), v12.V4S()); in GenerateTestSequenceNEON()
2208 __ uadalp(v28.V2S(), v12.V4H()); in GenerateTestSequenceNEON()
2209 __ uadalp(v0.V4H(), v17.V8B()); in GenerateTestSequenceNEON()
2210 __ uadalp(v1.V4S(), v29.V8H()); in GenerateTestSequenceNEON()
2211 __ uadalp(v15.V8H(), v22.V16B()); in GenerateTestSequenceNEON()
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| H A D | test-cpu-features-aarch64.cc | 2466 TEST_NEON(uadalp_0, uadalp(v0.V4H(), v1.V8B()))
2467 TEST_NEON(uadalp_1, uadalp(v0.V8H(), v1.V16B()))
2468 TEST_NEON(uadalp_2, uadalp(v0.V2S(), v1.V4H()))
2469 TEST_NEON(uadalp_3, uadalp(v0.V4S(), v1.V8H()))
2470 TEST_NEON(uadalp_4, uadalp(v0.V1D(), v1.V2S()))
2471 TEST_NEON(uadalp_5, uadalp(v0.V2D(), v1.V4S()))
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| H A D | test-api-movprfx-aarch64.cc | 2295 __ uadalp(z20.VnD(), p4.Merging(), z5.VnS()); in TEST()
3476 __ uadalp(z20.VnD(), p4.Merging(), z20.VnS()); in TEST()
3658 __ uadalp(z20.VnD(), p4.Merging(), z5.VnS()); in TEST()
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| H A D | test-simulator-aarch64.cc | 4875 DEFINE_TEST_NEON_2DIFF_LONG(uadalp, Basic)
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| H A D | test-disasm-sve-aarch64.cc | 7030 COMPARE(uadalp(z20.VnD(), p4.Merging(), z5.VnS()), in TEST()
7031 "uadalp z20.d, p4/m, z5.s"); in TEST()
7032 COMPARE(uadalp(z20.VnH(), p4.Merging(), z5.VnB()), in TEST()
7033 "uadalp z20.h, p4/m, z5.b"); in TEST()
7034 COMPARE(uadalp(z20.VnS(), p4.Merging(), z5.VnH()), in TEST()
7035 "uadalp z20.s, p4/m, z5.h"); in TEST()
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| /third_party/node/deps/v8/src/codegen/arm64/ |
| H A D | assembler-arm64.h | 1928 void uadalp(const VRegister& vd, const VRegister& vn);
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| H A D | macro-assembler-arm64.h | 313 V(uadalp, Uadalp) \
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| H A D | assembler-arm64.cc | 2009 void Assembler::uadalp(const VRegister& vd, const VRegister& vn) { in uadalp() function in v8::internal::Assembler
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| /third_party/node/deps/v8/src/execution/arm64/ |
| H A D | simulator-arm64.h | 1737 LogicVRegister uadalp(VectorFormat vform, LogicVRegister dst,
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| H A D | simulator-arm64.cc | 3996 uadalp(vf_lp, rd, rn);
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| H A D | simulator-logic-arm64.cc | 1971 LogicVRegister Simulator::uadalp(VectorFormat vform, LogicVRegister dst, in uadalp() function in v8::internal::Simulator
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| /third_party/vixl/src/aarch64/ |
| H A D | assembler-aarch64.h | 2986 void uadalp(const VRegister& vd, const VRegister& vn);
6640 void uadalp(const ZRegister& zda, const PRegisterM& pg, const ZRegister& zn);
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| H A D | simulator-aarch64.h | 3684 LogicVRegister uadalp(VectorFormat vform,
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| H A D | macro-assembler-aarch64.h | 3063 V(uadalp, Uadalp) \
7356 uadalp(zda, pg, zn); in Uadalp()
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| H A D | simulator-aarch64.cc | 3124 uadalp(vform, result, zn); in Simulator()
7026 uadalp(vf_lp, rd, rn); in Simulator()
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| H A D | assembler-aarch64.cc | 5317 void Assembler::uadalp(const VRegister& vd, const VRegister& vn) {
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| H A D | assembler-sve-aarch64.cc | 9064 void Assembler::uadalp(const ZRegister& zda, in uadalp() function in vixl::aarch64::Assembler
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| H A D | logic-aarch64.cc | 2484 LogicVRegister Simulator::uadalp(VectorFormat vform,
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