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Searched refs:tile_swizzle (Results 1 - 13 of 13) sorted by relevance

/third_party/mesa3d/src/gallium/drivers/radeonsi/
H A Dsi_sdma_copy_image.c183 radeon_emit((uint32_t)tiled_address | (tiled->surface.tile_swizzle << 8)); in si_sdma_v4_v5_copy_texture()
239 unsigned dst_tile_swizzle = dst_mode == RADEON_SURF_MODE_2D ? sdst->surface.tile_swizzle : 0; in cik_sdma_copy_texture()
240 unsigned src_tile_swizzle = src_mode == RADEON_SURF_MODE_2D ? ssrc->surface.tile_swizzle : 0; in cik_sdma_copy_texture()
H A Dsi_texture.c708 if (sscreen->ws->buffer_is_suballocated(res->buf) || tex->surface.tile_swizzle || in si_texture_get_handle()
717 assert(tex->surface.tile_swizzle == 0); in si_texture_get_handle()
1649 assert(tex->surface.tile_swizzle == 0); in si_texture_from_winsys_buffer()
H A Dsi_compute_blit.c842 ((uint32_t)tex->surface.tile_swizzle << 16); in gfx9_clear_dcc_msaa()
H A Dsi_state.c3283 unsigned dcc_tile_swizzle = tex->surface.tile_swizzle; in si_emit_framebuffer_state()
3293 cb_color_base |= tex->surface.tile_swizzle; in si_emit_framebuffer_state()
3319 cb_color_base |= tex->surface.tile_swizzle; in si_emit_framebuffer_state()
3366 cb_color_base |= tex->surface.tile_swizzle; in si_emit_framebuffer_state()
3405 cb_color_base |= tex->surface.tile_swizzle; in si_emit_framebuffer_state()
H A Dsi_descriptors.c319 state[0] |= tex->surface.tile_swizzle; in si_set_mutable_tex_desc_fields()
330 unsigned dcc_tile_swizzle = tex->surface.tile_swizzle << 8; in si_set_mutable_tex_desc_fields()
/third_party/mesa3d/src/amd/vulkan/
H A Dradv_sdma_copy_image.c143 (uint32_t)tiled_address | (image->planes[0].surface.tile_swizzle << 8)); in radv_sdma_v4_v5_copy_image_to_buffer()
H A Dradv_image.c789 state[0] |= plane->surface.tile_swizzle; in si_set_mutable_tex_desc_fields()
801 unsigned dcc_tile_swizzle = plane->surface.tile_swizzle << 8; in si_set_mutable_tex_desc_fields()
H A Dradv_device.c6291 cb->cb_color_base |= surf->tile_swizzle; in radv_initialise_color_surface()
6298 cb->cb_color_base |= surf->tile_swizzle; in radv_initialise_color_surface()
6337 unsigned dcc_tile_swizzle = surf->tile_swizzle; in radv_initialise_color_surface()
/third_party/mesa3d/src/amd/common/
H A Dac_surface.h348 uint8_t tile_swizzle; member
H A Dac_surface.c947 u_bit_consecutive(0, sizeof(surf->tile_swizzle) * 8)); in gfx6_surface_settings()
948 surf->tile_swizzle = AddrBaseSwizzleOut.tileSwizzle; in gfx6_surface_settings()
1358 assert(xout.tileSwizzle <= u_bit_consecutive(0, sizeof(surf->tile_swizzle) * 8)); in gfx6_compute_surface()
1371 * the miptree uses non-zero tile_swizzle. Otherwise there are in gfx6_compute_surface()
1879 assert(xout.pipeBankXor <= u_bit_consecutive(0, sizeof(surf->tile_swizzle) * 8)); in gfx9_compute_miptree()
1880 surf->tile_swizzle = xout.pipeBankXor; in gfx9_compute_miptree()
2000 assert(surf->tile_swizzle == 0); in gfx9_compute_miptree()
/third_party/mesa3d/src/gallium/drivers/r600/
H A Dr600_texture.c496 rtex->surface.tile_swizzle) { in r600_texture_get_handle()
503 assert(rtex->surface.tile_swizzle == 0); in r600_texture_get_handle()
652 out->tile_swizzle = fmask.tile_swizzle; in r600_texture_get_fmask_info()
1145 assert(rtex->surface.tile_swizzle == 0); in r600_texture_from_handle()
H A Dr600_pipe_common.h185 unsigned tile_swizzle; member
/third_party/mesa3d/src/gallium/winsys/radeon/drm/
H A Dradeon_drm_surface.c404 surf_ws->fmask_tile_swizzle = fmask.tile_swizzle; in radeon_winsys_surface_init()

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