Searched refs:thrsw (Results 1 - 10 of 10) sorted by relevance
| /third_party/mesa3d/src/broadcom/compiler/ |
| H A D | qpu_schedule.c | 391 if (inst->sig.thrsw) { in calculate_deps()
1016 merge.sig.thrsw |= b->sig.thrsw; in qpu_merge_inst()
1070 if (prev_inst->inst->qpu.sig.thrsw) in choose_instruction_to_schedule()
1131 /* If we are in a thrsw delay slot check that this instruction in choose_instruction_to_schedule()
1168 if (inst->sig.thrsw) in choose_instruction_to_schedule()
1201 * it in the delay slots of a thrsw, which is not in choose_instruction_to_schedule()
1575 * This is called when trying to merge a thrsw back into the instruction stream
1576 * of instructions that were scheduled *before* the thrsw signal to fill its
1577 * delay slots. Because the actual execution of the thrsw happen
2506 struct qinst *thrsw = vir_nop(); v3d_qpu_schedule_instructions() local
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| H A D | vir_opt_redundant_flags.c | 111 /* Flags aren't preserved across a thrsw. in vir_opt_redundant_flags_block()
116 if (inst->qpu.sig.thrsw) in vir_opt_redundant_flags_block()
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| H A D | qpu_validate.c | 236 if (inst->sig.thrsw) { in qpu_validate_inst()
245 * last-thrsw signal. in qpu_validate_inst()
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| H A D | vir_dump.c | 220 if (sig->thrsw) in vir_dump_sig()
221 fprintf(stderr, "; thrsw"); in vir_dump_sig()
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| H A D | nir_to_vir.c | 164 c->last_thrsw->qpu.sig.thrsw = true; in vir_emit_thrsw()
4457 if (inst->qpu.sig.thrsw) in vir_remove_thrsw()
4467 * start of the last thread section, which may include adding a new thrsw
4497 * thrsw. in vir_emit_last_thrsw()
4534 struct qinst *thrsw, in vir_restore_last_thrsw()
4539 c->last_thrsw = thrsw; in vir_restore_last_thrsw()
4533 vir_restore_last_thrsw(struct v3d_compile *c, struct qinst *thrsw, bool scoreboard_lock) vir_restore_last_thrsw() argument
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| H A D | vir_register_allocate.c | 287 * thrsw. in v3d_choose_spill_node()
414 * thrsw
416 * If the sequence is for a spill, then it will emit a tmuwt after the thrsw,
421 * due to the new thrsw itroduced in the sequence above.
434 * we are consuming it immediately without thrsw in between. in v3d_emit_spill_tmua()
470 * is not affected by the thrsw. Something that ends at ip will be in v3d_emit_spill_tmua()
711 /* Make sure c->last_thrsw is the actual last thrsw, not just one we in v3d_spill_reg()
788 * invalidated through thrsw), so running out of physical registers in v3d_ra_favor_accum()
1062 if (inst->qpu.sig.thrsw) { in update_graph_and_reg_classes_for_inst()
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| H A D | vir.c | 84 inst->qpu.sig.thrsw) { in vir_has_side_effects()
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| /third_party/mesa3d/src/broadcom/qpu/ |
| H A D | qpu_disasm.c | 206 if (!sig->thrsw && in v3d_qpu_disasm_sig()
222 if (sig->thrsw) in v3d_qpu_disasm_sig()
223 append(disasm, "; thrsw"); in v3d_qpu_disasm_sig()
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| H A D | qpu_instr.h | 43 bool thrsw:1; member
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| H A D | qpu_pack.c | 107 #define THRSW .thrsw = true
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