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Searched refs:tg4 (Results 1 - 4 of 4) sorted by relevance

/third_party/mesa3d/src/gallium/drivers/freedreno/a4xx/
H A Dfd4_emit.c203 unsigned num_textures = tex->num_textures + v->astc_srgb.count + v->tg4.count; in emit_textures()
261 for (i = 0; i < v->tg4.count; i++) { in emit_textures()
264 unsigned idx = v->tg4.orig_idx[i]; in emit_textures()
343 assert(v->tg4.count == 0); in emit_textures()
929 cp->tg4.count; in fd4_emit_cs_state()
/third_party/mesa3d/src/freedreno/ir3/
H A Dir3_shader.h337 /* per-component (3-bit) swizzles of each sampler (a4xx tg4): */
707 /* for tg4 workaround, the number/base of additional
713 } tg4; member
H A Dir3_compiler_nir.c3217 array_insert(ctx->ir, ctx->ir->tg4, sam); in emit_tex()
3256 tex->op != nir_texop_tg4 && /* leave out tg4, unless it's on alpha? */ in emit_tex()
4453 /* Fixup tex sampler state for tg4 workaround instructions. We
4469 so->tg4.base = tex_idx; in fixup_tg4()
4472 struct ir3_instruction *sam = ctx->ir->tg4[i]; in fixup_tg4()
4479 so->tg4.orig_idx[idx++] = sam->cat5.tex; in fixup_tg4()
4480 so->tg4.count++; in fixup_tg4()
H A Dir3.h537 /* Track tg4 instructions which need texture state patched in (for tg4
540 DECLARE_ARRAY(struct ir3_instruction *, tg4);

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