/third_party/node/deps/v8/src/diagnostics/arm/ |
H A D | disasm-arm.cc | 1120 Format(instr, "sxtb'cond 'rd, 'rm"); in DecodeType3() 1123 Format(instr, "sxtb'cond 'rd, 'rm, ror #8"); in DecodeType3() 1126 Format(instr, "sxtb'cond 'rd, 'rm, ror #16"); in DecodeType3() 1129 Format(instr, "sxtb'cond 'rd, 'rm, ror #24"); in DecodeType3()
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/third_party/vixl/test/aarch32/ |
H A D | test-assembler-cond-rd-operand-rn-t32.cc | 60 M(sxtb) \ 342 #include "aarch32/traces/assembler-cond-rd-operand-rn-sxtb-t32.h"
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H A D | test-assembler-cond-rd-operand-rn-a32.cc | 60 M(sxtb) \ 1117 #include "aarch32/traces/assembler-cond-rd-operand-rn-sxtb-a32.h"
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H A D | test-assembler-cond-rd-operand-rn-ror-amount-a32.cc | 52 M(sxtb) \ 1317 #include "aarch32/traces/assembler-cond-rd-operand-rn-ror-amount-sxtb-a32.h"
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H A D | test-assembler-cond-rd-operand-rn-ror-amount-t32.cc | 52 M(sxtb) \ 1205 #include "aarch32/traces/assembler-cond-rd-operand-rn-ror-amount-sxtb-t32.h"
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/third_party/vixl/src/aarch32/ |
H A D | assembler-aarch32.h | 3571 void sxtb(Condition cond, 3575 void sxtb(Register rd, const Operand& operand) { in sxtb() function in vixl::aarch32::Assembler 3576 sxtb(al, Best, rd, operand); in sxtb() 3578 void sxtb(Condition cond, Register rd, const Operand& operand) { in sxtb() function in vixl::aarch32::Assembler 3579 sxtb(cond, Best, rd, operand); in sxtb() 3581 void sxtb(EncodingSize size, Register rd, const Operand& operand) { in sxtb() function in vixl::aarch32::Assembler 3582 sxtb(al, size, rd, operand); in sxtb()
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H A D | disasm-aarch32.h | 1353 void sxtb(Condition cond,
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H A D | disasm-aarch32.cc | 3261 void Disassembler::sxtb(Condition cond, in sxtb() function in vixl::aarch32::Disassembler 8062 sxtb(CurrentCond(), in DecodeT32() 20795 sxtb(CurrentCond(), in DecodeT32() 20804 sxtb(CurrentCond(), in DecodeT32() [all...] |
H A D | assembler-aarch32.cc | 12636 void Assembler::sxtb(Condition cond, in sxtb() function in vixl::aarch32::Assembler 12679 Delegate(kSxtb, &Assembler::sxtb, cond, size, rd, operand); in sxtb()
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H A D | macro-assembler-aarch32.h | 5674 sxtb(cond, rd, operand); in MacroAssembler()
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/third_party/node/deps/v8/src/wasm/baseline/arm64/ |
H A D | liftoff-assembler-arm64.h | 1532 sxtb(dst.W(), src.W()); in emit_i32_signextend_i8() 1541 sxtb(dst.gp(), src.gp()); in emit_i64_signextend_i8()
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/third_party/node/deps/v8/src/codegen/arm64/ |
H A D | macro-assembler-arm64-inl.h | 962 sxtb(rd, rn); in Sxtb()
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H A D | assembler-arm64.h | 638 void sxtb(const Register& rd, const Register& rn) { sbfm(rd, rn, 0, 7); }
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/third_party/node/deps/v8/src/codegen/arm/ |
H A D | assembler-arm.h | 575 void sxtb(Register dst, Register src, int rotate = 0, Condition cond = al);
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H A D | assembler-arm.cc | 1932 void Assembler::sxtb(Register dst, Register src, int rotate, Condition cond) { in sxtb() function in v8::internal::Assembler
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/third_party/vixl/test/aarch64/ |
H A D | test-disasm-aarch64.cc | 337 COMPARE(adds(w15, w16, Operand(w17, SXTB, 4)), "adds w15, w16, w17, sxtb #4"); in TEST() 338 COMPARE(add(x18, x19, Operand(x20, SXTB, 3)), "add x18, x19, w20, sxtb #3"); in TEST() 363 COMPARE(subs(w15, w16, Operand(w17, SXTB, 4)), "subs w15, w16, w17, sxtb #4"); in TEST() 364 COMPARE(sub(x18, x19, Operand(x20, SXTB, 3)), "sub x18, x19, w20, sxtb #3"); in TEST() 368 COMPARE(cmp(w0, Operand(w1, SXTB, 1)), "cmp w0, w1, sxtb #1"); in TEST() 528 COMPARE(sxtb(w0, w1), "sxtb w0, w1"); in TEST() 529 COMPARE(sxtb(x2, x3), "sxtb x2, w3"); in TEST() 533 COMPARE(sxtb(x in TEST() [all...] |
H A D | test-api-movprfx-aarch64.cc | 274 __ sxtb(z28.VnS(), p6.Merging(), z28.VnS()); in TEST() 834 __ sxtb(z26.VnS(), p5.Merging(), z17.VnS()); in TEST() 1612 __ sxtb(z5.VnD(), p6.Merging(), z20.VnD()); in TEST()
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H A D | test-trace-aarch64.cc | 349 __ sxtb(w8, w9); in GenerateTestSequenceBase() 350 __ sxtb(x10, x11); in GenerateTestSequenceBase()
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H A D | test-disasm-sve-aarch64.cc | 2986 COMPARE(sxtb(z19.VnH(), p7.Merging(), z3.VnH()), "sxtb z19.h, p7/m, z3.h"); in TEST() 2987 COMPARE(sxtb(z3.VnS(), p1.Merging(), z17.VnS()), "sxtb z3.s, p1/m, z17.s"); in TEST() 2988 COMPARE(sxtb(z27.VnD(), p0.Merging(), z12.VnD()), "sxtb z27.d, p0/m, z12.d"); in TEST() 3000 COMPARE(dci(0x0410a000), "unallocated (Unallocated)"); // sxtb b in TEST()
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H A D | test-cpu-features-aarch64.cc | 497 TEST_NONE(sxtb_0, sxtb(w0, w1)) 498 TEST_NONE(sxtb_1, sxtb(x0, w1))
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/third_party/vixl/src/aarch64/ |
H A D | assembler-aarch64.h | 842 void sxtb(const Register& rd, const Register& rn) { sbfm(rd, rn, 0, 7); } in sxtb() function in vixl::aarch64::Assembler 5659 void sxtb(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn);
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H A D | macro-assembler-aarch64.h | 2611 sxtb(rd, rn); in Sxtb() 6220 sxtb(zd, pg, zn); in Sxtb()
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H A D | assembler-sve-aarch64.cc | 3472 void Assembler::sxtb(const ZRegister& zd, in sxtb() function in vixl::aarch64::Assembler
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/third_party/node/deps/v8/src/compiler/backend/arm/ |
H A D | code-generator-arm.cc | 1156 __ sxtb(i.OutputRegister(), i.InputRegister(0), i.InputInt32(1)); in AssembleArchInstruction() 3357 __ sxtb(i.OutputRegister(0), i.OutputRegister(0)); in AssembleArchInstruction() 3377 __ sxtb(i.OutputRegister(0), i.OutputRegister(0)); in AssembleArchInstruction() 3406 __ sxtb(i.OutputRegister(0), i.OutputRegister(0)); \ in AssembleArchInstruction()
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/third_party/node/deps/v8/src/wasm/baseline/arm/ |
H A D | liftoff-assembler-arm.h | 2180 sxtb(dst, src); in emit_i32_signextend_i8()
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