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Searched refs:subgroup_size (Results 1 - 25 of 36) sorted by relevance

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/third_party/mesa3d/src/vulkan/runtime/
H A Dvk_pipeline.c107 enum gl_subgroup_size subgroup_size; in vk_pipeline_shader_stage_to_nir() local
112 subgroup_size = req_subgroup_size; in vk_pipeline_shader_stage_to_nir()
116 subgroup_size = SUBGROUP_SIZE_VARYING; in vk_pipeline_shader_stage_to_nir()
119 subgroup_size = SUBGROUP_SIZE_FULL_SUBGROUPS; in vk_pipeline_shader_stage_to_nir()
121 subgroup_size = SUBGROUP_SIZE_API_CONSTANT; in vk_pipeline_shader_stage_to_nir()
125 info->pName, subgroup_size, in vk_pipeline_shader_stage_to_nir()
H A Dvk_nir.c82 enum gl_subgroup_size subgroup_size, in vk_spirv_to_nir()
94 spirv_options_local.subgroup_size = subgroup_size; in vk_spirv_to_nir()
79 vk_spirv_to_nir(struct vk_device *device, const uint32_t *spirv_data, size_t spirv_size_B, gl_shader_stage stage, const char *entrypoint_name, enum gl_subgroup_size subgroup_size, const VkSpecializationInfo *spec_info, const struct spirv_to_nir_options *spirv_options, const struct nir_shader_compiler_options *nir_options, void *mem_ctx) vk_spirv_to_nir() argument
H A Dvk_nir.h43 enum gl_subgroup_size subgroup_size,
/third_party/mesa3d/src/intel/compiler/
H A Dbrw_simd_selection.c33 if ((int)info->subgroup_size >= (int)SUBGROUP_SIZE_REQUIRE_8) { in brw_required_dispatch_width()
38 return (unsigned)info->subgroup_size; in brw_required_dispatch_width()
H A Dbrw_nir.c1368 switch (info->subgroup_size) { in get_subgroup_size()
1404 return info->subgroup_size; in get_subgroup_size()
1427 .subgroup_size = get_subgroup_size(&nir->info, max_subgroup_size), in brw_nir_apply_key()
/third_party/mesa3d/src/compiler/nir/
H A Dnir_lower_subgroups.c476 nir_ssa_def *subgroup_size = nir_load_subgroup_size(b); in build_subgroup_mask() local
482 subgroup_size)); in build_subgroup_mask()
492 * with a target ballot type of 4 x uint32 and subgroup_size = 64 we'd need in build_subgroup_mask()
496 * "ballot_bit_size - subgroup_size" is also a multiple of in build_subgroup_mask()
512 return nir_bcsel(b, nir_ult(b, min_idx_val, subgroup_size), in build_subgroup_mask()
631 if (options->subgroup_size) in lower_subgroups_instr()
632 return nir_imm_int(b, options->subgroup_size); in lower_subgroups_instr()
816 if (options->subgroup_size && in lower_subgroups_instr()
817 nir_intrinsic_cluster_size(intrin) >= options->subgroup_size) { in lower_subgroups_instr()
/third_party/mesa3d/src/freedreno/ir3/
H A Dir3_nir.c476 unsigned subgroup_size = 0, max_subgroup_size = 0; in ir3_nir_post_finalize() local
479 subgroup_size = max_subgroup_size = compiler->threadsize_base; in ir3_nir_post_finalize()
482 subgroup_size = max_subgroup_size = compiler->threadsize_base * 2; in ir3_nir_post_finalize()
486 * Lower subgroup_size here, to avoid having to deal with it when in ir3_nir_post_finalize()
492 subgroup_size = max_subgroup_size = compiler->threadsize_base; in ir3_nir_post_finalize()
494 subgroup_size = 0; in ir3_nir_post_finalize()
502 .subgroup_size = subgroup_size, in ir3_nir_post_finalize()
/third_party/mesa3d/src/compiler/spirv/
H A Dnir_spirv.h79 enum gl_subgroup_size subgroup_size; member
/third_party/mesa3d/src/amd/compiler/
H A Daco_shader_info.h143 uint8_t subgroup_size; member
H A Daco_instruction_selection_setup.cpp406 if (ctx->shader->info.stage == MESA_SHADER_COMPUTE && ctx->program->info.cs.subgroup_size) { in init_context()
407 ctx->ub_config.min_subgroup_size = ctx->program->info.cs.subgroup_size; in init_context()
408 ctx->ub_config.max_subgroup_size = ctx->program->info.cs.subgroup_size; in init_context()
/third_party/mesa3d/src/gallium/frontends/clover/core/
H A Ddevice.hpp86 cl_uint subgroup_size() const;
H A Ddevice.cpp402 device::subgroup_size() const { in subgroup_size() function in device
/third_party/mesa3d/src/compiler/
H A Dshader_info.h240 enum gl_subgroup_size subgroup_size; member
/third_party/mesa3d/src/freedreno/vulkan/
H A Dtu_pipeline.h189 uint32_t subgroup_size; member
/third_party/mesa3d/src/amd/vulkan/
H A Dradv_aco_shader_info.h101 ASSIGN_FIELD(cs.subgroup_size); in radv_aco_convert_shader_info()
H A Dradv_pipeline.c3397 return info->cs.subgroup_size; in radv_get_wave_size()
3410 if (stage == MESA_SHADER_COMPUTE && info->cs.subgroup_size) in radv_get_ballot_bit_size()
3411 return info->cs.subgroup_size; in radv_get_ballot_bit_size()
3641 unsigned subgroup_size = pipeline_key->cs.compute_subgroup_size; in radv_fill_shader_info() local
3642 unsigned req_subgroup_size = subgroup_size; in radv_fill_shader_info()
3645 if (!subgroup_size) in radv_fill_shader_info()
3646 subgroup_size = device->physical_device->cs_wave_size; in radv_fill_shader_info()
3662 subgroup_size = RADV_SUBGROUP_SIZE; in radv_fill_shader_info()
3665 stages[MESA_SHADER_COMPUTE].info.cs.subgroup_size = subgroup_size; in radv_fill_shader_info()
7234 const VkPipelineShaderStageRequiredSubgroupSizeCreateInfo *subgroup_size = radv_generate_compute_pipeline_key() local
[all...]
H A Dradv_shader.h353 uint8_t subgroup_size; member
H A Dradv_shader.c674 unsigned subgroup_size = 64, ballot_bit_size = 64; in radv_shader_spirv_to_nir() local
680 subgroup_size = key->cs.compute_subgroup_size; in radv_shader_spirv_to_nir()
963 .subgroup_size = subgroup_size, in radv_shader_spirv_to_nir()
/third_party/mesa3d/src/gallium/drivers/llvmpipe/
H A Dlp_screen.c546 uint32_t *subgroup_size = ret; in llvmpipe_get_compute_param() local
547 *subgroup_size = 32; in llvmpipe_get_compute_param()
/third_party/mesa3d/src/gallium/drivers/radeonsi/
H A Dsi_shader_nir.c266 .subgroup_size = 64, in si_lower_nir()
H A Dsi_get.c941 uint32_t *subgroup_size = ret; in si_get_compute_param() local
942 *subgroup_size = si_determine_wave_size(sscreen, NULL); in si_get_compute_param()
/third_party/mesa3d/src/mesa/main/
H A Dglspirv.c247 .subgroup_size = SUBGROUP_SIZE_UNIFORM, in _mesa_spirv_to_nir()
/third_party/mesa3d/src/gallium/frontends/clover/api/
H A Dkernel.cpp176 buf.as_scalar<size_t>() = dev.subgroup_size(); in clGetKernelWorkGroupInfo()
/third_party/mesa3d/src/gallium/drivers/r600/
H A Dr600_pipe_common.c1046 uint32_t *subgroup_size = ret; in r600_get_compute_param() local
1047 *subgroup_size = r600_wavefront_size(rscreen->family); in r600_get_compute_param()
/third_party/mesa3d/src/intel/vulkan/
H A Danv_pipeline.c1865 stage.nir->info.subgroup_size == SUBGROUP_SIZE_API_CONSTANT && in anv_pipeline_compile_cs()
1868 stage.nir->info.subgroup_size = SUBGROUP_SIZE_FULL_SUBGROUPS; in anv_pipeline_compile_cs()
1876 if (stage.nir->info.subgroup_size == SUBGROUP_SIZE_FULL_SUBGROUPS) in anv_pipeline_compile_cs()
1877 stage.nir->info.subgroup_size = BRW_SUBGROUP_SIZE; in anv_pipeline_compile_cs()
2709 trampoline_nir->info.subgroup_size = SUBGROUP_SIZE_REQUIRE_8; in anv_device_init_rt_shaders()

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