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Searched refs:sub0 (Results 1 - 25 of 27) sorted by relevance

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/third_party/skia/third_party/externals/oboe/samples/RhythmGame/third_party/glm/simd/
H A Dcommon.h94 glm_ivec4 const sub0 = _mm_sub_epi32(inv0, sgn0); in glm_ivec4_abs()
95 return sub0; in glm_ivec4_abs()
119 glm_vec4 const sub0 = glm_vec4_sub(add0, or0); in glm_vec4_round()
120 return sub0; in glm_vec4_round()
132 glm_vec4 const sub0 = glm_vec4_sub(rnd0, and0); in glm_vec4_floor()
133 return sub0; in glm_vec4_floor()
151 glm_vec4 const sub0 = glm_vec4_sub(add0, or0); in glm_vec4_roundEven() local
152 return sub0; in glm_vec4_roundEven()
171 glm_vec4 const sub0 = glm_vec4_sub(x, flr0); in glm_vec4_fract() local
172 return sub0; in glm_vec4_fract()
180 glm_vec4 const sub0 = glm_vec4_sub(x, mul0); glm_vec4_mod() local
193 glm_vec4 const sub0 = glm_vec4_sub(_mm_set1_ps(1.0f), a); glm_vec4_mix() local
207 glm_vec4 const sub0 = glm_vec4_sub(x, edge0); glm_vec4_smoothstep() local
[all...]
H A Dgeometric.h22 glm_vec4 const sub0 = _mm_sub_ps(p0, p1); in glm_vec4_distance() local
23 glm_vec4 const len0 = glm_vec4_length(sub0); in glm_vec4_distance()
73 glm_vec4 const sub0 = _mm_sub_ps(mul0, mul1); in glm_vec4_cross() local
74 return sub0; in glm_vec4_cross()
99 glm_vec4 const sub0 = _mm_sub_ps(I, mul1); in glm_vec4_reflect() local
100 return sub0; in glm_vec4_reflect()
108 glm_vec4 const sub0 = _mm_sub_ps(_mm_set1_ps(1.0f), mul0); in glm_vec4_refract() local
110 glm_vec4 const mul2 = _mm_mul_ps(sub0, sub1); in glm_vec4_refract()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
H A DSIMachineFunctionInfo.cpp191 getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SGPR_128RegClass)); in addPrivateSegmentBuffer()
198 getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass)); in addDispatchPtr()
205 getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass)); in addQueuePtr()
213 getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass)); in addKernargSegmentPtr()
220 getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass)); in addDispatchID()
227 getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass)); in addFlatScratchInit()
234 getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass)); in addImplicitBufferPtr()
H A DSIInstrInfo.cpp1429 Register DstLo = RI.getSubReg(Dst, AMDGPU::sub0); in expandPostRAPseudo()
1446 .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub0)) in expandPostRAPseudo()
1493 unsigned SubReg = AMDGPU::sub0 + MI.getOperand(3).getImm(); in expandPostRAPseudo()
1515 Register RegLo = RI.getSubReg(Reg, AMDGPU::sub0); in expandPostRAPseudo()
1585 for (auto Sub : { AMDGPU::sub0, AMDGPU::sub1 }) { in expandMovDPP64()
1622 .addImm(AMDGPU::sub0) in expandMovDPP64()
1802 .addReg(PCReg, RegState::Define, AMDGPU::sub0) in insertIndirectBranch()
1803 .addReg(PCReg, 0, AMDGPU::sub0) in insertIndirectBranch()
1812 .addReg(PCReg, RegState::Define, AMDGPU::sub0) in insertIndirectBranch()
1813 .addReg(PCReg, 0, AMDGPU::sub0) in insertIndirectBranch()
[all...]
H A DSIRegisterInfo.cpp113 return getMatchingSuperReg(BaseReg, AMDGPU::sub0, &AMDGPU::SGPR_128RegClass);
1132 ConstOffsetReg = getSubReg(MIB.getReg(1), AMDGPU::sub0); in eliminateFrameIndex()
1480 // %2 = REG_SEQUENCE %0, sub0, %1, sub1, %2, sub2
1481 // %3 = COPY %2, sub0
1508 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3,
1519 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3,
1526 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3,
1531 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3, AMDGPU::sub4,
1535 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3,
1539 AMDGPU::sub0, AMDGP
[all...]
H A DAMDGPUInstructionSelector.cpp231 case AMDGPU::sub0: in getSubOperand64()
342 MachineOperand Lo1(getSubOperand64(I.getOperand(1), HalfRC, AMDGPU::sub0)); in selectG_ADD_SUB()
343 MachineOperand Lo2(getSubOperand64(I.getOperand(2), HalfRC, AMDGPU::sub0)); in selectG_ADD_SUB()
378 .addImm(AMDGPU::sub0) in selectG_ADD_SUB()
1227 return AMDGPU::sub0;
1238 return AMDGPU::sub0;
1388 .addImm(AMDGPU::sub0)
1475 .addImm(AMDGPU::sub0)
1679 .addReg(SrcReg, 0, AMDGPU::sub0);
1688 .addImm(AMDGPU::sub0)
[all...]
H A DSIAddIMGInit.cpp116 static_assert(AMDGPU::sub0 == 1 && AMDGPU::sub4 == 5, "Subreg indices different from expected"); in runOnMachineFunction()
H A DGCNRegBankReassign.cpp284 Reg = TRI->getSubReg(Reg, AMDGPU::sub0);
311 Reg = TRI->getSubReg(Reg, AMDGPU::sub0);
448 PhysReg = TRI->getSubReg(PhysReg, AMDGPU::sub0);
H A DAMDGPURegisterInfo.cpp31 { AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3,
H A DSIFrameLowering.cpp216 Register FlatScrInitLo = TRI->getSubReg(FlatScratchInitReg, AMDGPU::sub0); in emitFlatScratchInit()
546 Register RsrcLo = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0); in emitEntryFunctionScratchSetup()
641 Register Rsrc0 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0); in emitEntryFunctionScratchSetup()
H A DAMDGPUISelDAGToDAG.cpp652 SDValue(Lo, 0), CurDAG->getTargetConstant(AMDGPU::sub0, DL, MVT::i32), in buildSMovImm64()
817 SubReg0 = CurDAG->getTargetConstant(AMDGPU::sub0, DL, MVT::i32); in Select()
1008 SDValue Sub0 = CurDAG->getTargetConstant(AMDGPU::sub0, DL, MVT::i32); in SelectADD_SUB_I64()
1706 SDValue Sub0 = CurDAG->getTargetConstant(AMDGPU::sub0, DL, MVT::i32); in SelectFlatOffset()
1811 CurDAG->getTargetConstant(AMDGPU::sub0, SL, MVT::i32), in Expand32BitAddress()
2204 unsigned SubReg = Is32 ? AMDGPU::sub0 : AMDGPU::sub0_sub1; in SelectATOMIC_CMP_SWAP()
H A DR600MachineScheduler.cpp260 case R600::sub0: in getAluKind()
H A DSIISelLowering.cpp3332 return std::make_pair(AMDGPU::sub0, Offset); in computeIndirectRegAndOffset()
3334 return std::make_pair(AMDGPU::sub0 + Offset, 0); in computeIndirectRegAndOffset()
3545 .addImm(SubReg - AMDGPU::sub0); in emitIndirectDst()
3578 .addImm(SubReg - AMDGPU::sub0); in emitIndirectDst()
3620 Src0, BoolRC, AMDGPU::sub0, in EmitInstrWithCustomInserter()
3627 Src1, BoolRC, AMDGPU::sub0, in EmitInstrWithCustomInserter()
3645 .addImm(AMDGPU::sub0) in EmitInstrWithCustomInserter()
3774 .addReg(Src0, 0, AMDGPU::sub0) in EmitInstrWithCustomInserter()
3776 .addReg(Src1, 0, AMDGPU::sub0) in EmitInstrWithCustomInserter()
3787 .addImm(AMDGPU::sub0) in EmitInstrWithCustomInserter()
[all...]
H A DSILoadStoreOptimizer.cpp968 unsigned SubRegIdx0 = (CI.EltSize == 4) ? AMDGPU::sub0 : AMDGPU::sub0_sub1; in mergeRead2Pair()
1460 {AMDGPU::sub0, AMDGPU::sub0_sub1, AMDGPU::sub0_sub1_sub2, AMDGPU::sub0_sub1_sub2_sub3}, in getSubRegIdxs()
1636 .addImm(AMDGPU::sub0) in computeBase()
1680 // REG_SEQUENCE %LO:vgpr_32, %subreg.sub0, %HI:vgpr_32, %subreg.sub1
/third_party/icu/icu4j/main/classes/core/src/com/ibm/icu/util/
H A DLocaleData.java435 String sub0 = "{0}"; in getLocaleSeparator()
439 int index0 = localeSeparator.indexOf(sub0); in getLocaleSeparator()
442 return localeSeparator.substring(index0 + sub0.length(), index1); in getLocaleSeparator()
/third_party/icu/ohos_icu4j/src/main/java/ohos/global/icu/util/
H A DLocaleData.java420 String sub0 = "{0}"; in getLocaleSeparator()
424 int index0 = localeSeparator.indexOf(sub0); in getLocaleSeparator()
427 return localeSeparator.substring(index0 + sub0.length(), index1); in getLocaleSeparator()
/third_party/python/Lib/idlelib/idle_test/
H A Dtest_browser.py156 sub0, sub1 = mbt.GetSubList()
158 self.assertIsInstance(sub0, browser.ChildBrowserTreeItem)
160 self.assertEqual(sub0.name, 'f0')
/third_party/lzma/CPP/7zip/Common/
H A DFilterCoder.h15 #define Z7_COM_QI_ENTRY_AG(i, sub0, sub) else if (iid == IID_ ## i) \
16 { if (!sub) RINOK(sub0->QueryInterface(IID_ ## i, (void **)&sub)) \
/third_party/icu/icu4c/source/i18n/
H A Dulocdata.cpp336 static const UChar sub0[4] = { 0x007b, 0x0030, 0x007d , 0x0000 }; /* {0} */ in ulocdata_getLocaleSeparator() local
374 p0=u_strstr(separator, sub0); in ulocdata_getLocaleSeparator()
/third_party/node/deps/icu-small/source/i18n/
H A Dulocdata.cpp347 static const char16_t sub0[4] = { 0x007b, 0x0030, 0x007d , 0x0000 }; /* {0} */ in ulocdata_getLocaleSeparator() local
390 p0=u_strstr(separator, sub0); in ulocdata_getLocaleSeparator()
/third_party/skia/third_party/externals/icu/source/i18n/
H A Dulocdata.cpp333 static const UChar sub0[4] = { 0x007b, 0x0030, 0x007d , 0x0000 }; /* {0} */ in ulocdata_getLocaleSeparator() local
371 p0=u_strstr(separator, sub0); in ulocdata_getLocaleSeparator()
/third_party/skia/third_party/externals/icu/source/common/
H A Dlocdispnames.cpp482 static const UChar sub0[4] = { 0x007b, 0x0030, 0x007d , 0x0000 } ; /* {0} */ in uloc_getDisplayName() local
548 UChar *p0=u_strstr(separator, sub0); in uloc_getDisplayName()
565 UChar *p0=u_strstr(pattern, sub0); in uloc_getDisplayName()
/third_party/icu/icu4c/source/common/
H A Dlocdispnames.cpp494 static const UChar sub0[4] = { 0x007b, 0x0030, 0x007d , 0x0000 } ; /* {0} */ in uloc_getDisplayName() local
560 UChar *p0=u_strstr(separator, sub0); in uloc_getDisplayName()
577 UChar *p0=u_strstr(pattern, sub0); in uloc_getDisplayName()
/third_party/node/deps/icu-small/source/common/
H A Dlocdispnames.cpp494 static const char16_t sub0[4] = { 0x007b, 0x0030, 0x007d , 0x0000 } ; /* {0} */ in uloc_getDisplayName() local
560 char16_t *p0=u_strstr(separator, sub0); in uloc_getDisplayName()
577 char16_t *p0=u_strstr(pattern, sub0); in uloc_getDisplayName()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/Disassembler/
H A DAMDGPUDisassembler.cpp545 unsigned VdataSub0 = MRI.getSubReg(Vdata0, AMDGPU::sub0); in convertMIMGInst()
548 NewVdata = MRI.getMatchingSuperReg(Vdata0, AMDGPU::sub0, in convertMIMGInst()
561 unsigned VAddrSub0 = MRI.getSubReg(VAddr0, AMDGPU::sub0); in convertMIMGInst()
565 NewVAddr0 = MRI.getMatchingSuperReg(VAddr0, AMDGPU::sub0, in convertMIMGInst()

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