| /third_party/ffmpeg/libavcodec/aarch64/ |
| H A D | vc1dsp_neon.S | 45 ssra v20.8h, v19.8h, #2 // 4 * src[24] + 16 * src[40]
48 ssra v7.8h, v22.8h, #2 // 16 * src[8] + 4 * src[56]
52 ssra v1.8h, v1.8h, #1 // 12/2 * src[0]
53 ssra v5.8h, v5.8h, #1 // 12/2 * src[32]
77 ssra v22.8h, v7.8h, #1 // (t5 + t1) >> 1
78 ssra v1.8h, v19.8h, #1 // (t7 - t3) >> 1
80 ssra v5.8h, v4.8h, #1 // (t6 + t2) >> 1
81 ssra v16.8h, v6.8h, #1 // (t7 + t3) >> 1
82 ssra v2.8h, v18.8h, #1 // (t8 - t4) >> 1
83 ssra v1
[all...] |
| /third_party/vixl/test/aarch64/ |
| H A D | test-trace-aarch64.cc | 1785 __ ssra(d12, d28, 44); in GenerateTestSequenceNEON()
1786 __ ssra(v29.V16B(), v31.V16B(), 4); in GenerateTestSequenceNEON()
1787 __ ssra(v3.V2D(), v0.V2D(), 24); in GenerateTestSequenceNEON()
1788 __ ssra(v14.V2S(), v28.V2S(), 6); in GenerateTestSequenceNEON()
1789 __ ssra(v18.V4H(), v8.V4H(), 7); in GenerateTestSequenceNEON()
1790 __ ssra(v31.V4S(), v14.V4S(), 24); in GenerateTestSequenceNEON()
1791 __ ssra(v28.V8B(), v26.V8B(), 5); in GenerateTestSequenceNEON()
1792 __ ssra(v9.V8H(), v9.V8H(), 14); in GenerateTestSequenceNEON()
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| H A D | test-cpu-features-aarch64.cc | 1995 TEST_NEON(ssra_0, ssra(v0.V8B(), v1.V8B(), 5))
1996 TEST_NEON(ssra_1, ssra(v0.V16B(), v1.V16B(), 7))
1997 TEST_NEON(ssra_2, ssra(v0.V4H(), v1.V4H(), 14))
1998 TEST_NEON(ssra_3, ssra(v0.V8H(), v1.V8H(), 6))
1999 TEST_NEON(ssra_4, ssra(v0.V2S(), v1.V2S(), 12))
2000 TEST_NEON(ssra_5, ssra(v0.V4S(), v1.V4S(), 4))
2001 TEST_NEON(ssra_6, ssra(v0.V2D(), v1.V2D(), 16))
2002 TEST_NEON(ssra_7, ssra(d0, d1, 53))
|
| H A D | test-disasm-sve-aarch64.cc | 6398 COMPARE(ssra(z0.VnB(), z8.VnB(), 1), "ssra z0.b, z8.b, #1"); in TEST()
6399 COMPARE(ssra(z0.VnB(), z8.VnB(), 2), "ssra z0.b, z8.b, #2"); in TEST()
6400 COMPARE(ssra(z0.VnB(), z8.VnB(), 5), "ssra z0.b, z8.b, #5"); in TEST()
6401 COMPARE(ssra(z0.VnB(), z8.VnB(), 8), "ssra z0.b, z8.b, #8"); in TEST()
6402 COMPARE(ssra(z0.VnH(), z8.VnH(), 1), "ssra z in TEST()
[all...] |
| H A D | test-simulator-aarch64.cc | 2470 // test for shift and accumulate instructions (srsra/ssra/usra/ursra). in Test2OpImmNEON_Helper()
4774 DEFINE_TEST_NEON_2OPIMM(ssra, Basic, TypeWidth)
4809 DEFINE_TEST_NEON_2OPIMM_SCALAR_D(ssra, Basic, TypeWidth)
|
| H A D | test-api-movprfx-aarch64.cc | 2280 __ ssra(z0.VnB(), z8.VnB(), 1); in TEST()
3081 __ ssra(z0.VnB(), z8.VnB(), 1); in TEST()
3461 __ ssra(z0.VnB(), z0.VnB(), 1); in TEST()
|
| /third_party/node/deps/v8/src/codegen/arm64/ |
| H A D | assembler-arm64.h | 1360 void ssra(const VRegister& vd, const VRegister& vn, int shift);
|
| H A D | macro-assembler-arm64.h | 1239 V(ssra, Ssra) \
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| H A D | assembler-arm64.cc | 1719 void Assembler::ssra(const VRegister& vd, const VRegister& vn, int shift) { in ssra() function in v8::internal::Assembler
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| /third_party/vixl/src/aarch64/ |
| H A D | macro-assembler-sve-aarch64.cc | 2236 ShiftRightAccumulate(&Assembler::ssra, zd, za, zn, shift); in Ssra()
|
| H A D | assembler-aarch64.h | 3231 void ssra(const VRegister& vd, const VRegister& vn, int shift);
6583 void ssra(const ZRegister& zda, const ZRegister& zn, int shift);
|
| H A D | simulator-aarch64.cc | 3232 ssra(vform, zd, zn, shift_dist); in Simulator()
9351 ssra(vf, rd, rn, right_shift); in Simulator()
9454 ssra(vf, rd, rn, right_shift); in Simulator()
|
| H A D | simulator-aarch64.h | 4196 LogicVRegister ssra(VectorFormat vform,
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| H A D | assembler-aarch64.cc | 5661 void Assembler::ssra(const VRegister& vd, const VRegister& vn, int shift) {
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| H A D | assembler-sve-aarch64.cc | 8757 void Assembler::ssra(const ZRegister& zda, const ZRegister& zn, int shift) { in ssra() function in vixl::aarch64::Assembler
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| H A D | logic-aarch64.cc | 1763 LogicVRegister Simulator::ssra(VectorFormat vform,
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| H A D | macro-assembler-aarch64.h | 3180 V(ssra, Ssra) \
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| /third_party/node/deps/v8/src/execution/arm64/ |
| H A D | simulator-arm64.h | 1917 LogicVRegister ssra(VectorFormat vform, LogicVRegister dst,
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| H A D | simulator-arm64.cc | 5768 ssra(vf, rd, rn, right_shift);
5867 ssra(vf, rd, rn, right_shift);
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| H A D | simulator-logic-arm64.cc | 1472 LogicVRegister Simulator::ssra(VectorFormat vform, LogicVRegister dst, in ssra() function in v8::internal::Simulator
|