| /third_party/ffmpeg/libavcodec/aarch64/ |
| H A D | vc1dsp_neon.S | 163 srsra v23.8h, v16.8h, #1 // (t8 - t4 + 1) >> 1
164 srsra v22.8h, v5.8h, #1 // (t7 - t3 + 1) >> 1
165 srsra v1.8h, v17.8h, #1 // (t6 - t2 + 1) >> 1
166 srsra v6.8h, v3.8h, #1 // (t5 - t1 + 1) >> 1
419 srsra v0.4h, v2.4h, #1 // (t8 - t4 + 1) >> 1
421 srsra v22.4h, v21.4h, #1 // (t7 - t3 + 1) >> 1
423 srsra v3.4h, v24.4h, #1 // (t6 - t2 + 1) >> 1
425 srsra v1.4h, v16.4h, #1 // (t5 - t1 + 1) >> 1
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| /third_party/vixl/test/aarch64/ |
| H A D | test-trace-aarch64.cc | 1755 __ srsra(d21, d30, 63); in GenerateTestSequenceNEON()
1756 __ srsra(v27.V16B(), v30.V16B(), 6); in GenerateTestSequenceNEON()
1757 __ srsra(v20.V2D(), v12.V2D(), 27); in GenerateTestSequenceNEON()
1758 __ srsra(v0.V2S(), v17.V2S(), 5); in GenerateTestSequenceNEON()
1759 __ srsra(v14.V4H(), v16.V4H(), 15); in GenerateTestSequenceNEON()
1760 __ srsra(v18.V4S(), v3.V4S(), 20); in GenerateTestSequenceNEON()
1761 __ srsra(v21.V8B(), v1.V8B(), 1); in GenerateTestSequenceNEON()
1762 __ srsra(v31.V8H(), v25.V8H(), 2); in GenerateTestSequenceNEON()
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| H A D | test-cpu-features-aarch64.cc | 1965 TEST_NEON(srsra_0, srsra(v0.V8B(), v1.V8B(), 4))
1966 TEST_NEON(srsra_1, srsra(v0.V16B(), v1.V16B(), 2))
1967 TEST_NEON(srsra_2, srsra(v0.V4H(), v1.V4H(), 13))
1968 TEST_NEON(srsra_3, srsra(v0.V8H(), v1.V8H(), 6))
1969 TEST_NEON(srsra_4, srsra(v0.V2S(), v1.V2S(), 4))
1970 TEST_NEON(srsra_5, srsra(v0.V4S(), v1.V4S(), 1))
1971 TEST_NEON(srsra_6, srsra(v0.V2D(), v1.V2D(), 17))
1972 TEST_NEON(srsra_7, srsra(d0, d1, 16))
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| H A D | test-disasm-sve-aarch64.cc | 6409 COMPARE(srsra(z0.VnB(), z8.VnB(), 1), "srsra z0.b, z8.b, #1"); in TEST()
6410 COMPARE(srsra(z0.VnB(), z8.VnB(), 2), "srsra z0.b, z8.b, #2"); in TEST()
6411 COMPARE(srsra(z0.VnB(), z8.VnB(), 5), "srsra z0.b, z8.b, #5"); in TEST()
6412 COMPARE(srsra(z0.VnB(), z8.VnB(), 8), "srsra z0.b, z8.b, #8"); in TEST()
6413 COMPARE(srsra(z0.VnH(), z8.VnH(), 1), "srsra z in TEST()
[all...] |
| H A D | test-simulator-aarch64.cc | 2470 // test for shift and accumulate instructions (srsra/ssra/usra/ursra). in Test2OpImmNEON_Helper()
4776 DEFINE_TEST_NEON_2OPIMM(srsra, Basic, TypeWidth)
4811 DEFINE_TEST_NEON_2OPIMM_SCALAR_D(srsra, Basic, TypeWidth)
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| H A D | test-api-movprfx-aarch64.cc | 2277 __ srsra(z0.VnB(), z8.VnB(), 1); in TEST()
3078 __ srsra(z0.VnB(), z8.VnB(), 1); in TEST()
3458 __ srsra(z0.VnB(), z0.VnB(), 1); in TEST()
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| /third_party/node/deps/v8/src/codegen/arm64/ |
| H A D | assembler-arm64.h | 1366 void srsra(const VRegister& vd, const VRegister& vn, int shift);
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| H A D | macro-assembler-arm64.h | 1235 V(srsra, Srsra) \
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| H A D | assembler-arm64.cc | 1729 void Assembler::srsra(const VRegister& vd, const VRegister& vn, int shift) { in srsra() function in v8::internal::Assembler
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| /third_party/vixl/src/aarch64/ |
| H A D | macro-assembler-sve-aarch64.cc | 2229 ShiftRightAccumulate(&Assembler::srsra, zd, za, zn, shift); in Srsra()
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| H A D | assembler-aarch64.h | 3237 void srsra(const VRegister& vd, const VRegister& vn, int shift);
6574 void srsra(const ZRegister& zda, const ZRegister& zn, int shift);
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| H A D | simulator-aarch64.cc | 3229 srsra(vform, zd, zn, shift_dist); in Simulator()
9357 srsra(vf, rd, rn, right_shift); in Simulator()
9460 srsra(vf, rd, rn, right_shift); in Simulator()
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| H A D | simulator-aarch64.h | 4204 LogicVRegister srsra(VectorFormat vform,
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| H A D | assembler-aarch64.cc | 5675 void Assembler::srsra(const VRegister& vd, const VRegister& vn, int shift) {
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| H A D | assembler-sve-aarch64.cc | 8715 void Assembler::srsra(const ZRegister& zda, const ZRegister& zn, int shift) { in srsra() function in vixl::aarch64::Assembler
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| H A D | logic-aarch64.cc | 1783 LogicVRegister Simulator::srsra(VectorFormat vform,
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| H A D | macro-assembler-aarch64.h | 3178 V(srsra, Srsra) \
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| /third_party/node/deps/v8/src/execution/arm64/ |
| H A D | simulator-arm64.h | 1921 LogicVRegister srsra(VectorFormat vform, LogicVRegister dst,
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| H A D | simulator-arm64.cc | 5774 srsra(vf, rd, rn, right_shift);
5873 srsra(vf, rd, rn, right_shift);
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| H A D | simulator-logic-arm64.cc | 1486 LogicVRegister Simulator::srsra(VectorFormat vform, LogicVRegister dst, in srsra() function in v8::internal::Simulator
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